---
title: 'Principal Physical Verification Engineer at Celero Communications, Inc.'
canonical: 'https://feeny.ai/job/principal-physical-verification-engineer-celero-communications-inc-san-jose-ey6w6ckb1anx'
type: 'job'
last_seen: '2026-10-16'
---

# Principal Physical Verification Engineer at Celero Communications, Inc.

- **Company:** Celero Communications, Inc.
- **Location:** San Jose, CA
- **Posted:** 2026-09-21
- **Last confirmed live:** 2026-10-16
- **Apply:** https://job-boards.greenhouse.io/celerocommunicationsinc/jobs/4414105009

## Job description

Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure. We recently announced a $275M Series C following the validation of the industry’s first 2nm coherent DSP silicon. Bloomberg also reported that Alphabet’s CapitalG has backed Celero at a $3B valuation. As we continue to grow, we’re hiring exceptional talent across the United States, Canada, and Argentina for a variety of exciting opportunities.

We are seeking a Full-Chip Physical Verification Engineer to join our Physical Design team and help deliver complex digital blocks and full-chip implementations in advanced process technologies. This role will own all aspects of Physical Verification execution on advanced TSMC nodes, ensuring design quality, manufacturability, and tapeout readiness. The ideal candidate has successfully completed multiple tapeouts and brings deep expertise in physical verification methodologies, including driving improvements in quality, execution efficiency, and predictable delivery across multiple programs. You will work closely with the Analog Design and Physical Design teams to identify and resolve verification challenges while ensuring designs meet aggressive performance, manufacturability, and schedule objectives.

## Key Responsibilities

## Team & Project Leadership

- Lead full chip Physical Verification effort
- Own execution plans, schedules for full-chip
- Drive accountability for quality, milestones, and tapeout readiness.
- Conduct full chip and blocks PV checks

Physical Verification Ownership

- Ownership of full chip verification
- Work with internal analog team to ensure clean IP delivery
- Responsible for running and analyzing DRC/ERC/LUP/PERC results
- Experience with using either ICV or Calibre verification tools
- Understanding advance TSMC DRC rules

Cross-Functional Collaboration

- Partner with analog, block, chip top owners to ensure clean floorplan
- Provide early guidance on corner case requirements
- Influence floorplan constraints, hierarchy, and implementation strategy
- Participate in tapeout readiness reviews

Required Qualifications

- Bachelor’s or Master’s degree in Electrical Engineering or related field.
- 7+ years of experience with full-chip verifications

Proven hands-on experience with:

- Physical Verification tools (Synopsys IC Validator (ICV), Siemens Calibre)
- Able to assemble a flow to support block/chip level PV

Strong expertise in:

- Floorplanning to avoid DRC/LVS issues
- Provide guidance to analog IP team to allow for clean integration

## Preferred Qualifications

- Experience in advanced technology nodes (7nm, 5nm, 3nm)
- Automation skills using Tcl, Python, or shell scripting

Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)

## About Celero Communications, Inc.

## Company Overview
- **One-liner**: Celero Communications develops advanced coherent DSP solutions that enable high-bandwidth, low-power optical connectivity for AI infrastructure, eliminating distance bottlenecks in data centers.
- **Entity Type**: Private (Series B; total funding $148.4M per LinkedIn, $140M per company press release)
- **Headquarters**: Irvine, California, USA
- **Founded**: 2024
- **Founders**: Nariman Yousefi (CEO, President & Co-founder) and Oscar Agazzi (CTO & Co-founder)

## Core Business
- **Primary industry**: Semiconductor manufacturing / optical networking for AI infrastructure
- **Target customers**: B2B – hyperscale data centers, AI cloud providers, and large-scale accelerated computing clusters
- **Mission**: “Deliver the optical performance and scalability needed for the next generation of accelerated computing” [celero.inc](https://celero.inc/about/)

## Products & Services
- **Coherent DSP Platform**: A digital signal processor that provides light-speed performance, bandwidth efficiency, and scalable optical links for AI accelerators, servers, and clusters. The technology is described as 100x more efficient than conventional optical transmission and is designed for interoperability across diverse AI and cloud platforms. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/)

## Market Standing
- **Valuation**: Not publicly disclosed
- **Key Metric**: Total funding of **$148.4 million** (Seed $8.4M led by Sutter Hill Ventures; Venture Round $40M; Series B $100M led by CapitalG) [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Notable Investors/Partners**: Sutter Hill Ventures (lead seed & Series A), CapitalG (lead Series B), plus other undisclosed investors in venture round [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Growth Signals**: Founded in 2024, already employs **93 people** with a monthly headcount growth of **+9.3%**. Operates design centers in Irvine (CA), Ottawa (Canada), and Córdoba (Argentina). [linkedin.com](https://www.linkedin.com/company/celero-communications)

## Competitive Advantages
- **Founding team** consists of industry pioneers from Marvell, Inphi, Broadcom, and ClariPhy with decades of experience in analog design, digital signal processing, and optical networking. [celero.inc](https://celero.inc/about/)
- **Coherent DSP technology** that eliminates distance bottlenecks, delivering 100x more efficient optical transmission for scale-across AI infrastructure. [celero.inc](https://celero.inc/)
- **System flexibility and interoperability** across diverse AI and cloud platforms, making it easier for data centers to adopt. [celero.inc](https://celero.inc/)

## Strategic Focus
- **Current priorities**: Scaling AI infrastructure connectivity by delivering high-bandwidth, low-power optical links; expanding engineering teams across all design centers; and building energy-efficient systems that redefine how data centers connect. [celero.inc](https://celero.inc/careers/)

## Why Work Here
- **Culture**: Described as driven by curiosity, precision, and the challenge of making AI systems faster and more energy-efficient. Employees collaborate with global experts in coherent DSP and optical engineering. [celero.inc](https://celero.inc/careers/)
- **Work model**: On-site/hybrid at three locations – Irvine, CA (HQ); Ottawa, Canada; and Córdoba, Argentina. Multiple engineering roles (Analog Design, ASIC, DSP, Firmware, Verification) are posted with specific location requirements. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc)
- **Notable perks**: Opportunity to work on next-generation AI infrastructure technology alongside industry pioneers. The company emphasizes building scalable, energy-efficient systems and offers roles across R&D, operations, and manufacturing. [celero.inc](https://celero.inc/careers/)

## Sources
1. [celero.inc](https://celero.inc/) – Company homepage and product description
2. [celero.inc](https://celero.inc/about/) – About page (founding, leadership, mission)
3. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/) – Press release on $140M funding
4. [linkedin.com](https://www.linkedin.com/company/celero-communications) – LinkedIn company page (funding details, headcount, locations, employee breakdown)
5. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc) – Careers page (open positions, locations)

## Other roles at Celero Communications, Inc.

- [Office Manager & Administrative Coordinator](https://feeny.ai/job/office-manager-administrative-coordinator-celero-communications-inc-ottawa-wxg395zknksm) — Ottawa, Canada
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-abktjq9g2jgw) — Ottawa, Canada
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-4kasvranjrvf) — San Jose, CA
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-vnzcs82knnj6) — Irvine, CA
- [High-Speed Analog Layout Design Engineer](https://feeny.ai/job/high-speed-analog-layout-design-engineer-celero-communications-inc-cordoba-k9yg56pm5h0s) — Córdoba, Argentina
- [Principal Physical Design Engineer](https://feeny.ai/job/principal-physical-design-engineer-celero-communications-inc-san-jose-j8296q80qyrn) — San Jose, CA
- [Principal Physical Design Engineer](https://feeny.ai/job/principal-physical-design-engineer-celero-communications-inc-irvine-65y1r1ktv2qt) — Irvine, CA
- [Principal Physical Verification Engineer](https://feeny.ai/job/principal-physical-verification-engineer-celero-communications-inc-irvine-phzd6q5fk38s) — Irvine, CA
- [Principal DFT Engineer](https://feeny.ai/job/principal-dft-engineer-celero-communications-inc-irvine-qj862e757kcv) — Irvine, CA
- [ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal](https://feeny.ai/job/asic-design-engineer-digital-dsp-design-analog-mixed-signal-celero-pd4fx2w60yhv) — Ottawa, Canada