---
title: 'Principal Platform Security Architect at Neurophos'
canonical: 'https://feeny.ai/job/principal-platform-security-architect-neurophos-sunnyvale-fw052b83t93h'
type: 'job'
last_seen: '2026-09-07'
---

# Principal Platform Security Architect at Neurophos

- **Company:** Neurophos
- **Location:** Sunnyvale, CA
- **Compensation:** $250k–$300k
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-08-11
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.ashbyhq.com/neurophos/bf7cbee8-2349-4f0f-97c2-3ffd3e01c35f

## Job description

## ABOUT NEUROPHOS

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A https://www.neurophos.com/110m-raise led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

Location: Austin, TX or Sunnyvale, CA. Full-time onsite position.

Reports To: VP of Architecture

FLSA Status: Exempt

## POSITION OVERVIEW

We are seeking a Principal Platform Security Architect to own platform security across our electronic integrated circuit (EIC) and the wider T100 system. This is a product security role, not an IT or corporate security role. Hyperscale customers will not deploy an accelerator they cannot verify, so this position owns the machinery that makes our silicon verifiable: the root of trust, secure and measured boot, device attestation, signed firmware update, and security telemetry. The ideal candidate has shipped these subsystems on real silicon, can speak fluently to both RTL designers and firmware engineers, and knows the datacenter compliance landscape well enough to design toward it rather than retrofit for it. This role is the technical owner for our outsourced root-of-trust subsystem engagement.

## KEY RESPONSIBILITIES

- Own the platform threat model and the security architecture that answers it, from fab through field deployment.
- Architect the silicon root of trust: RoT IP integration, key provisioning, fuse and one-time programmable (OTP) strategy, and debug authorization.
- Define the secure and measured boot chain and firmware resiliency behavior.
- Own device attestation using SPDM (Security Protocol and Data Model) with DICE (Device Identifier Composition Engine) identity.
- Define signed over-the-air (OTA) firmware update with anti-rollback protection.
- Specify security-relevant telemetry and its exposure to datacenter operators.
- Drive compliance against OCP (Open Compute Project) security profiles and DMTF (Distributed Management Task Force) specifications.
- Own the key management lifecycle and the associated manufacturing and field processes.
- Serve as technical owner for the outsourced root-of-trust subsystem engagement.
- Support customer and hyperscaler security reviews, and own the security narrative in those forums.
- Partner with digital design, firmware, and systems teams to land security requirements in implementation.

## QUALIFICATIONS

- BS/MS/PhD in Computer Science, Electrical Engineering, or a related field.
- 10+ years in hardware and firmware security architecture on silicon that shipped.
- Hands-on experience integrating root-of-trust IP, including provisioning and fuse/OTP planning.
- Secure boot chain design and firmware resiliency to NIST SP 800-193 class requirements.
- Working knowledge of SPDM, DICE, MCTP (Management Component Transport Protocol), and PLDM (Platform Level Data Model).
- Practical understanding of cryptographic primitives, key hierarchies, and secure key storage in silicon.
- Demonstrated ability to write security specifications that digital design and firmware teams can implement against.
- Excellent communication skills and comfort defending architectural decisions to external reviewers.

## PREFERRED SKILLS

- Familiarity with OCP Security profiles and Caliptra.
- Side-channel and fault-injection countermeasure design.
- FIPS or Common Criteria certification experience.
- Experience supporting hyperscaler security review processes.
- Background in confidential computing or trusted execution environments.
- Post-quantum cryptography migration planning.
- Experience with manufacturing-side provisioning flows and supply chain security.

## WHAT WE OFFER

This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.

## BENEFITS

Join a team that invests in your future and your well-being. At Neurophos, we offer:

- 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
- Unlimited PTO. No rigid vacation banks, just a focus on delivery.
- 401(k) matching and stock option opportunities to ensure our success is your success.
- Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
- Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

## About Neurophos

## Company Overview
- **One-liner**: Neurophos develops photonic AI chips (Optical Processing Units) that perform matrix multiplications at the speed of light, aiming to replace traditional GPUs in data-center inference workloads.
- **Entity Type**: Private, Series A
- **Headquarters**: Austin, Texas, USA (with an additional office in San Jose, California)
- **Founded**: 2020
- **Founders**: Patrick Bowen (CEO, Co-Founder) and Andrew Traverso (Chief Scientist, Co-Founder); other co-founders may include Preston Woo and Hod Finkelstein (CEO, CTO roles indicated on team page).

## Core Business
- **Primary industry**: Semiconductor / Photonic AI Hardware
- **Target customers**: B2B – hyperscale data centers, enterprise AI infrastructure providers
- **Mission/purpose**: “We’re building the first programmable light-speed computer” – solving energy and scalability challenges in AI data centers by using optical rather than electronic computation.

## Products & Services
- **Optical Processing Unit (OPU)**: A photonic AI chip that integrates over one million micron-scale optical processing components on a single die. It performs matrix multiplications in-memory at the speed of light, delivering up to 100x the energy efficiency of traditional GPUs and NVIDIA servers while fitting in a single-GPU form factor. The chip uses an active, programmable metasurface and silicon photonics to achieve 0.47 ExaOPS performance in a 1m x 1m footprint. First systems are targeted for early 2028, with production ramp in mid-2028.

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Total funding raised = **$119.2M** (including a $110M Series A closed in early 2026)
- **Notable Investors**: Gates Frontier (lead), M12 (Microsoft’s venture fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, MetaVC Partners, Gaingels, Mana Ventures, and 22+ others.
- **Growth Signals**: 
  - Recognized on EE Times Silicon 100 list for several consecutive years.
  - Over 300 patents filed and protected.
  - Rapid hiring after Series A – “hypergrowth phase” as per press release.
  - Team includes veterans from NVIDIA, AMD, Apple, Meta, Google, Magic Leap, Micron, Qualcomm, Samsung, and other photonic/AR companies.

## Competitive Advantages
- **Metasurface optical transistors** that are **10,000x smaller** than traditional photonic components, enabling unprecedented density – millions of weights fit in the area of a postage stamp.
- **300+ patents** covering optical metamaterials, neural network accelerators, and machine learning hardware.
- **Energy efficiency**: Up to 100x improvement over existing electronic solutions (e.g., GPUs), directly addressing the power constraints of hyperscale AI inference.
- **Size/performance**: OPU delivers the performance of a 3,000-pound server in the size and power envelope of a single GPU.

## Strategic Focus
- **Commercialization**: First customer evaluations begin in 2026; first OPU systems target early 2028 production ramp.
- **Talent acquisition**: Scaling the team aggressively across analog design, photonics, architecture, and software to meet “hypergrowth” demand.
- **Partnerships**: Leveraging investors like Bosch Ventures (industrial IoT), Aramco Ventures (energy), and M12 (cloud/AI) to align with large-scale data center customers.

## Why Work Here
- **Culture**: In-office, on‑site work culture in Austin, TX (primary) and San Jose, CA. Described as a “world-class team” with leaders from top semiconductor and tech companies.
- **Growth**: Joining at a hypergrowth scale‑up stage with significant funding and a clear path to production; opportunities to shape the architecture and engineering of a new computing paradigm.
- **Engineering focus**: 34 out of 40 total employees are in product + tech roles, indicating a highly technical, R&D-driven environment.
- **Impact**: Work on cutting-edge optical computing that could redefine AI hardware efficiency; involvement in everything from silicon photonics to compiler software.
- **Notable perks**: Not explicitly listed, but being a well-funded deep-tech startup likely offers competitive equity, technical challenges, and direct mentorship from industry veterans.

## Sources
1. [neurophos.com](https://www.neurophos.com/)
2. [neurophos.com/careers](https://www.neurophos.com/careers)
3. [neurophos.com/team](https://www.neurophos.com/team)
4. [cbinsights.com](https://www.cbinsights.com/company/neurophos)
5. [builtin.com](https://builtin.com/company/neurophos)

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