---
title: 'Principal RTL Design Engineer at SambaNova Systems'
canonical: 'https://feeny.ai/job/principal-rtl-design-engineer-sambanova-systems-austin-texas-xr2btm1h9adp'
type: 'job'
last_seen: '2026-09-08'
---

# Principal RTL Design Engineer at SambaNova Systems

- **Company:** SambaNova Systems
- **Location:** Austin Texas, United States / San Jose California, United States
- **Compensation:** $180k–$255k
- **Posted:** 2026-08-19
- **Last confirmed live:** 2026-09-08
- **Apply:** https://sambanova.ai/sambanova-available-positions/?gh_jid=6147579004

## Job description

The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale.

SambaNova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets.

## About the team

The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out, including RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with physical design.

## About the role

SambaNova is looking for a Principal RTL Design Engineer to own the microarchitecture and RTL for our next-generation Reconfigurable Dataflow Unit (RDU), the silicon behind our AI acceleration systems. This is a senior individual contributor role where you'll take a block from microarchitecture specification through RTL, quality closure, and tape-out, owning the power, performance, and area trade-offs along the way. Frequency targets are aggressive, so how you pipeline a datapath and where you spend area to buy timing are essential aspects of the role.

## Responsibilities

Some of your responsibilities will include:

- Own the microarchitecture and RTL for a major block or subsystem of the RDU, from specification through tape-out, including the specs you write for complex blocks in compute, memory, or on-chip network subsystems
- Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle
- Own PPA for your area, hitting aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring
- Drive timing closure and design quality for your area: synthesis, STA, critical-path iteration, lint, CDC, LEC, and SystemVerilog Assertions capturing design intent
- Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures
- Work with architects and software teams to prototype and evaluate features that improve application-level performance
- Drive AI, automation, and new EDA tool methodologies into the design flow
- Set the technical bar in design reviews and mentor design engineers

Required Qualifications

- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 7+ years of industry experience in ASIC RTL design
- Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent
- High-frequency design experience, including datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets
- Deep foundation in computer architecture and digital logic design, including arbitration, flow control, clock domain crossing, and memory structures
- Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC
- Experience converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team
- Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows
- Demonstrated technical leadership without formal authority, including setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers
- Scripting in Python for design and flow automation

## Preferred Qualifications

- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
- Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem
- Industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
- AI and ML workload acceleration techniques, and dataflow or reconfigurable architectures
- Formal property checking applied to design intent
- Advanced TSMC nodes and multi-die or chiplet design
- Performance modeling and analysis to support architectural trade-offs
- Fluency with Claude or other AI tools applied to RTL design and flow development

Base Salary Range:

Base Pay Range $180,000—$255,000 USD

Submission Guidelines Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.

## EEO Policy

SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.

## About SambaNova Systems

## Company Overview
- **One-liner**: SambaNova Systems provides a full-stack AI platform, from specialized Reconfigurable Dataflow Unit (RDU) chips to an agentic AI inference platform, designed for enterprises and governments.
- **Entity Type**: Private (Series E)
- **Headquarters**: San Jose, California, USA
- **Founded**: 2017
- **Founders**: Rodrigo Liang (Co-founder & CEO), Kunle Olukotun (Co-founder & Chief Technologist)

## Core Business
- **Primary Industry**: Artificial Intelligence / Enterprise AI Infrastructure
- **Target Customers**: Developers, large enterprises, government agencies, and data centers (B2B)
- **Mission Statement**: To be the most efficient and adaptable AI platform on the planet, empowering enterprises to control the trajectory of their data and AI future.

## Products & Services
- **SambaNova Suite**: The company's core product, a fully integrated AI platform that includes hardware, software, and models. It provides OpenAI-compatible APIs for inference.
- **SambaRack (SN40 & SN50)**: A state-of-the-art, rack-scale system optimized for AI inference. The SN50 is the fifth-generation system designed for fast agentic inference with high energy efficiency (average of 10 kWh for SN40).
- **Reconfigurable Dataflow Unit (RDU)**: A custom-designed AI chip (SN40L, SN50) with a unique three-tier memory architecture that delivers high speed and throughput for large models while using less power than traditional GPUs.
- **SambaOrchestrator**: A management tool for deploying, monitoring, and auto-scaling AI models across data centers.
- **Sovereign AI Platform**: An offering for governments and enterprises to keep data secure and governed while enabling business teams to use AI.

## Market Standing
- **Valuation/Market Cap**: Not publicly disclosed (Private company).
- **Key Metric**: Total funding of **$1.484B** (raised over multiple rounds, including a $350M Series E in early 2026).
- **Notable Investors/Partners**: Intel, GV (Google Ventures), BlackRock, Redline Capital Management, Atlantic Bridge Capital.
- **Growth Signals**: 
    - Raised a $350M Series E in early 2026.
    - A launch partner for Meta's Llama 4 series.
    - First platform to support all three variants of Llama 3.1 (8B, 70B, and 405B).
    - Has filed 313 patents related to parallel computing, computer memory, and instruction processing.
    - Customers include Blackbox and Texas Advanced Computing Center.

## Competitive Advantages
- **Full-Stack Integration**: Unlike many competitors, SambaNova controls the entire AI stack from the chip (RDU) to the software and models, allowing for deep optimization.
- **Efficiency**: The RDU's dataflow architecture is designed for high performance with significantly lower power consumption (best tokens per watt), a key differentiator for scaling AI.
- **Open-Source Focus**: The company is a strong supporter of open-source AI models, being a launch partner for major releases like Meta's Llama 4.

## Strategic Focus
- **Agentic AI**: The company is heavily focused on enabling complex, multi-step agentic AI workflows, with the SN50 chip and SambaOrchestrator built for this purpose.
- **Sovereign AI**: Targeting government and enterprise clients who need secure, on-premises or private cloud AI solutions.
- **Scaling Inference**: Prioritizing high-speed, low-latency inference for the largest open-source models (e.g., DeepSeek, Llama) at scale.

## Why Work Here
- **Culture**: Described as a "smart and motivated team" that values "talent first," "innovation that impacts," and "trust and integrity." The company emphasizes collaboration across departments and access to founders.
- **Work Environment**: Offers flexible working hours and a hybrid/remote-friendly policy (Flexible PTO in the U.S.).
- **Notable Perks**: 
    - Flexible PTO
    - Parental Leave
    - Medical, Dental, and Vision benefits
    - 401k/Pensions
    - Gym Access
    - Mentorship and buddy programs
    - Internship programs
- **Engineering Culture**: A deep-tech environment where you work on cutting-edge AI hardware (RDUs) and software, pushing the boundaries of AI performance.

## Sources
1. [SambaNova.ai](https://sambanova.ai/)
2. [SambaNova About Us](https://sambanova.ai/company/about)
3. [SambaNova Careers](https://sambanova.ai/company/careers)
4. [SambaNova Job Openings](https://sambanova.ai/company/careers/job-openings)
5. [CB Insights Profile](https://www.cbinsights.com/company/sambanova-systems)

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- [Senior Principal Runtime Engineer](https://feeny.ai/job/senior-principal-runtime-engineer-sambanova-systems-stockholm-g80m89md466t) — Stockholm, Sweden
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- [Senior RTL Design Engineer](https://feeny.ai/job/senior-rtl-design-engineer-sambanova-systems-austin-texas-dnhythpzwwkz) — Austin Texas, United States / San Jose California, United States