---
title: 'Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet at Astera Labs'
canonical: 'https://feeny.ai/job/principal-senior-principal-design-verification-engineer-cxl-pcie-ethernet-yzpz44j7h93t'
type: 'job'
last_seen: '2026-09-18'
---

# Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet at Astera Labs

- **Company:** Astera Labs
- **Location:** San Jose California, United States
- **Posted:** 2026-09-14
- **Last confirmed live:** 2026-09-18
- **Apply:** https://job-boards.greenhouse.io/asteralabs/jobs/4733819005

## Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/).

Principal / Senior Principal Design Verification Engineer – CXL / PCIe / Ethernet:

## Role Overview

We are seeking an experienced Principal / Senior Principal Design Verification Engineer to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success.

The ideal candidate is passionate about building world-class verification environments, has deep expertise in protocol verification, and enjoys solving complex architectural challenges.

## Key Responsibilities

Technical Leadership

- Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon.
- Define verification methodologies, reusable verification frameworks, and best practices across multiple programs.
- Drive verification planning, execution, coverage closure, and sign-off.
- Identify verification risks early and proactively drive mitigation plans.
- Lead technical reviews including architecture, RTL, verification, and tape-out readiness reviews.

Design Verification

- Architect and develop scalable UVM/System Verilog verification environments.
- Develop constrained-random, coverage-driven verification methodologies.
- Design scoreboards, protocol monitors, checkers, assertions (SVA), and functional coverage models.
- Debug complex RTL, protocol, timing, and integration issues.
- Drive regression planning, automation, and continuous integration improvements.
- Develop reusable VIP and verification infrastructure across multiple product lines.

Protocol Verification

Lead verification efforts involving one or more of:

- Compute Express Link (CXL 2.x / 3.x)
- PCI Express (Gen4/Gen5/Gen6)
- Ethernet (10G–800G)
- AXI, APB, AHB
- High-speed SerDes interfaces
- Memory interfaces including DDR/LPDDR/HBM (preferred)

Cross-Functional Collaboration

- Work closely with Architecture teams to influence design for verification.
- Partner with RTL designers during implementation and debug.
- Collaborate with Firmware, Emulation, FPGA, Post-Silicon Validation, and System Engineering teams.
- Support customer issue analysis and silicon bring-up when required.

Technical Mentorship

- Mentor and coach verification engineers across multiple experience levels.
- Establish verification standards and engineering excellence across the organization.
- Drive innovation in automation, verification productivity, and quality metrics.

Required Qualifications

- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- Minimum10+ years (Principal) or 15+ years (Senior Principal) of experience in Design Verification.
- Strong expertise in System Verilog and UVM.
- Extensive experience in verification planning, execution, and sign-off.
- Deep understanding of constrained-random verification and coverage-driven methodologies.
- Strong experience with assertions (SVA), functional coverage, and protocol compliance.
- Excellent debugging skills involving RTL, simulation, protocol analysis, and waveform debugging.
- Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.

## Preferred Technical Expertise

Strong experience in several of the following areas:

- CXL Cache, Memory, and I/O protocols
- PCIe Transaction, Data Link, and Physical Layers
- Ethernet MAC/PCS/PMA architecture
- Coherency protocols
- High-speed interconnects
- AI accelerator connectivity
- Data center SoC architecture
- Multi-chip and chiplet-based systems
- Performance verification
- Low-power verification
- CDC/RDC verification
- Formal Verification
- Portable Stimulus (PSS)
- Python, Perl, Tcl, or similar scripting languages
- Emulation and FPGA prototyping

Leadership Expectations

- Own technical direction for large verification programs.
- Influence architecture and product quality through early engagement.
- Drive cross-functional execution across geographically distributed teams.
- Establish reusable verification IP and methodology.
- Mentor engineers and help grow technical capability within the organization.
- Champion engineering excellence, quality, and continuous improvement.

## Preferred Experience

- Experience leading verification for large SoCs or complex connectivity IPs.
- Proven success delivering multiple first-pass silicon programs.
- Experience with AI infrastructure, cloud networking, or hyperscale data center technologies.
- Familiarity with customer-facing debug and post-silicon issue resolution.
- Contributions to verification methodology, reusable frameworks, or industry standards are a strong plus.

Salary range will be is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## About Astera Labs

## Company Overview
- **One-liner**: Astera Labs designs and delivers semiconductor-based connectivity solutions purpose-built to unleash the full potential of cloud and AI infrastructure.
- **Entity Type**: Public (Nasdaq: ALAB)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2017
- **Founders**: Jitendra Mohan, Sanjay Gajendra, Casey Morrison

## Core Business
- **Primary industry**: Semiconductor manufacturing / AI infrastructure connectivity
- **Target customers**: B2B, primarily hyperscale cloud providers and system OEMs (e.g., NVIDIA, AMD, Intel)
- **Mission statement**: To innovate, design, and deliver semiconductor-based connectivity solutions that are purpose-built to unleash the full potential of cloud and AI infrastructure.

## Products & Services
- **Aries PCIe®/CXL™ Smart DSP Retimers**: Silicon ICs, boards, and modules that digitally recover degraded high-speed signals to extend reach and enable higher PCIe/CXL data bandwidth between compute, storage, and network controllers.
- **Taurus Ethernet Smart Cable Modules™**: Hardware modules that increase network connectivity bandwidth between servers and switches over copper media, removing rack-level Ethernet bottlenecks.
- **Leo CXL Memory Connectivity Controllers**: ICs and boards that expand, share, and pool DRAM memory to overcome processor memory bandwidth bottlenecks for AI workloads.
- **Scorpio Smart Fabric Switches**: A family of PCIe 6 fabric switches ranging from 32 to 320 lanes, including the new 320-lane Scorpio X-Series Fabric Switch for AI scale-up fabrics.
- **COSMOS Software Suite**: A connectivity system management and optimization software that enables configuration, monitoring, troubleshooting, and predictive analytics for all Astera Labs products.

## Market Standing
- **Market Cap**: ~$11.6 billion (as of mid-2026)
- **Key Metric - Revenue**: $35 million (annual, reported)
- **Key Metric - Operating Income**: $173.4 million (2025)
- **Key Metric - Net Income**: $219.1 million (2025)
- **Total Funding**: ~$810.75 million (pre-IPO), with Series C ($50M, led by Fidelity) and Series D ($150M, led by Fidelity)
- **IPO Date**: March 20, 2024
- **Notable Investors/Partners**: Fidelity, NVIDIA, Advanced Micro Devices, Intel, major hyperscalers
- **Growth Signals**: 92% YoY headcount growth (675 employees); 144 active job postings (+260% YoY); expanded Taiwan operations with a new Cloud-Scale Interop Lab in 2026; shipping millions of devices across all major hyperscalers; 300+ design wins.

## Competitive Advantages
- **First-to-market innovation**: Pioneered first-to-market PCIe, Ethernet, and CXL connectivity products.
- **Patented software-defined platform approach**: Differentiates via a platform that combines silicon hardware with embedded COSMOS software, enabling flexibility, observability, and predictive analytics.
- **Deep hyperscaler relationships**: Trusted partner to the world’s largest cloud providers, with proven interoperability validated in their own Cloud-Scale Interop Lab.
- **Broad product portfolio**: Covers PCIe retimers, Ethernet cable modules, CXL memory controllers, and fabric switches—addressing the full spectrum of AI connectivity bottlenecks.
- **Strong IP and engineering talent**: 443 employees in technical roles; talent sourced from Intel (65), Marvell (37), Texas Instruments (40), AMD (22), and NVIDIA.

## Strategic Focus
- **Scaling AI infrastructure**: Expanding product portfolio and global footprint (12 countries) to meet surging demand for rack-scale AI.
- **Open standards leadership**: All products are grounded in open standards (PCIe, CXL, Ethernet), ensuring interoperability and broad adoption.
- **Taiwan expansion**: Growing engineering presence and Interop Lab in Taiwan to strengthen integration with leading AI platform providers and system manufacturers.
- **Continued innovation**: Shipping the new 320-lane Scorpio X-Series Fabric Switch and expanding the COSMOS software suite for fleet-level management and optimization.

## Why Work Here
- **Culture**: Described as collaborative, ownership-driven, and focused on solving complex problems together. The company emphasizes diversity and inclusion as drivers of creativity and innovation.
- **Growth**: Astera Labs supports non-linear career growth—employees can deepen expertise (“scale up”) or broaden into new areas (“scale out”). 92% YoY headcount growth signals rapid expansion and opportunity.
- **Remote/Hybrid**: Not explicitly stated, but global operations across 12 countries (including India, Canada, Israel, Taiwan, Vietnam) suggest a flexible, distributed work model.
- **Benefits**: Competitive medical, dental, and vision plans; flexible time off; family planning and parental leave; 401K and retirement plans.
- **Engineering culture**: Strong focus on cutting-edge semiconductor and AI infrastructure technology. High concentration of senior (24%) and specialist (19%) talent. Active internship and new graduate programs.
- **Employee ratings**: 4.5/5.0 on LinkedIn (124 reviews), with high marks for compensation (4.6), culture (4.4), and career development (4.4).

## Sources
1. [Astera Labs Careers Page](https://www.asteralabs.com/careers/)
2. [Astera Labs Official Website](https://www.asteralabs.com/)
3. [Astera Labs LinkedIn](https://www.linkedin.com/company/astera-labs)
4. [Astera Labs Products Page](https://www.asteralabs.com/products/)
5. [Astera Labs S-1 Filing (SEC)](https://ir.asteralabs.com/static-files/7103a4cb-aa6b-4f11-a4b0-f179cd4c5bee)

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