--- title: 'Principal Signal Integrity Engineer at d-Matrix' canonical: 'https://feeny.ai/job/principal-signal-integrity-engineer-d-matrix-santa-clara-q2wr2qfdtre5' type: 'job' last_seen: '2026-09-11' --- # Principal Signal Integrity Engineer at d-Matrix - **Company:** d-Matrix - **Location:** Santa Clara, CA - **Compensation:** $175k–$265k - **Employment:** full-time - **Work type:** hybrid - **Posted:** 2026-05-06 - **Last confirmed live:** 2026-09-11 - **Apply:** https://jobs.ashbyhq.com/d-matrix/70e72048-e196-4352-9d34-f93afc35c9d9/application **Skills:** Signal Integrity Design, Power Delivery Network (PDN) Design, Ansys HFSS, Cadence Sigrity, Keysight ADS, Simbeor, Ansys SIwave, Cadence PowerSI, CST, 112G SerDes, High-speed memory architectures, PAM4 signaling, Forward Error Correction (FEC), 50GHz+ VNAs, Time Domain Reflectometer (TDR), Oscilloscopes, IBIS-AMI models, PCB Material Science, Python, MATLAB > The Senior Staff SI/PI Engineer serves as the technical authority for electrical integrity in high-performance AI compute platforms. Responsibilities include leading end-to-end SI/PI modeling, simulation, and correlation for multi-chip modules, optimizing Power Delivery Networks, and mentoring hardware engineering t... ## Job description At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together, we can help shape the endless possibilities of AI. ## About the Role As the Senior Staff SI/PI Engineer, you will be the technical authority responsible for the electrical integrity of d-Matrix’s high-performance AI compute platforms. In an environment where we are pushing 112G/224G SerDes and delivering thousands of Amps to multi-chip modules (MCM), your role is critical to ensuring that our "Digital In-Memory Computing" architecture translates into stable, manufacturable, and world-class hardware. You will lead the end-to-end modeling, simulation, and correlation efforts—from the silicon die through the package and across the system PCBA. ## Key Responsibilities - End-to-End SI/PI Ownership: Drive the SI/PI strategy for next-generation AI accelerators, focusing on high-speed interfaces (PCIe Gen6/7, CXL, LPDDR5) and custom Chiplet-to-Chiplet interconnects. - MCM & Package Simulation: Lead the modeling and analysis of complex multi-chip packages, including interposer routing, micro-bump parasitic extraction, and die-to-die (D2D) link budgeting. - Advanced PDN Architecting: Design and optimize the Power Delivery Network (PDN) to meet stringent Z_Target requirements. Perform transient analysis to ensure voltage stability during massive AI workload swings. - Link Analysis & Budgeting: Perform comprehensive channel simulations (pre- and post-layout) using IBIS-AMI models. Define jitter, crosstalk, and loss budgets (insertion/return loss) for 112G+ channels. - Lab Correlation & Measurement: Lead the "Gold Suite" validation in the lab. Correlate simulation results with VNA, TDR, and high-speed oscilloscope measurements to close the loop on design accuracy. - Constraint Management: Translate complex simulation findings into actionable physical layout constraints for the PCB Design team, specifically for advanced stack-ups and high-density routing. - Technical Mentorship: Act as the subject matter expert, guiding hardware and layout engineers on SI/PI best practices and state-of-the-art mitigation techniques (e.g., skip-vias, voiding, material selection). Required Qualifications - Education: MS/PhD in Electrical Engineering or a related field with a focus on Electromagnetics or Signal Integrity. - Experience: 12+ years in SI/PI design for high-performance networking, GPUs, or server platforms. - Simulation Mastery: Expert-level proficiency in industry-standard tools: o SI: Ansys HFSS, Cadence Sigrity, Keysight ADS, or Simbeor. o PI: Ansys SIwave, Cadence PowerSI, or CST. - High-Speed Expertise: Proven track record with 112G SerDes and high-speed memory architectures. Deep understanding of PAM4 signaling and FEC (Forward Error Correction) impact on link margins. - Measurement Skills: Hands-on experience with 50GHz+ VNAs, TDRs, and real-time/sampling oscilloscopes. ## Preferred Skills - Knowledge of PCB Material Science (e.g., glass weave effects, skin effect loss, copper roughness modeling). - Experience with Python or MATLAB for post-processing large simulation datasets and automating sweep analysis. - Familiarity with OCP (Open Compute Project) hardware specifications for AI modules. ## Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation. ## About d-Matrix ## Company Overview - **One-liner**: d-Matrix is building ultra-low latency, memory-centric AI inference hardware and software platforms for datacenter-scale generative AI workloads. - **Entity Type**: Private (Series C, total raised ~$429M–$450M per conflicting reports) - **Headquarters**: Santa Clara, California, USA - **Founded**: 2019 - **Founders**: Sid Sheth (CEO) & Sudeep Bhoja (CTO / Founder) ## Core Business - **Primary industries**: AI infrastructure, semiconductor / hardware acceleration, datacenter compute - **Target customers**: Cloud providers, enterprises running large-scale generative AI inference (B2B) - **Mission / purpose**: To transform AI from unsustainable to attainable by breaking through limits of latency, cost, and energy in inference. ## Products & Services - **Corsair™** – AI inference accelerator platform (PCIe form factor, chiplet-based, 3D stacked DRAM) purpose-built for the decode phase of disaggregated inference. Works alongside GPUs for low-latency interactive AI. - **JetStream™** – Purpose-built I/O accelerator for AI inference (networking fabric to scale accelerator-to-accelerator communication). - **Aviator** – Software stack that orchestrates and optimizes inference workloads on d-Matrix hardware. - **SquadRack™** – Industry’s first rack-scale, disaggregated standards-based solution for AI inference, built with infrastructure partners. ## Market Standing - **Valuation**: Not publicly disclosed (private company) - **Key metric**: Total funding – $429M (per CB Insights) or $450M (per company blog after $275M Series C). Series C announced in late 2025 / early 2026. - **Notable investors**: Temasek, M12 (Microsoft’s venture arm), Playground Global, Nautilus Venture Partners, Industry Ventures, Mirae Asset Financial Group, Triatomic Capital, Bullhound Capital. - **Growth signals**: - Corsair entered full production in June 2026. - Won “AI Processor Innovation Award” from AI Breakthrough in June 2026. - Filed 21+ patents in parallel computing, neural networks, NLP. - Opened engineering offices in Santa Clara, Toronto, Bengaluru, Sydney, and Belgrade – global expansion underway. ## Competitive Advantages - **Memory-centric compute architecture (3DIMC™)** that eliminates latency bottlenecks caused by traditional memory-bound AI inference. - Chiplet-based design enables scaling to 100B+ parameter models in a PCIe form factor. - Disaggregated, standards-based rack-scale approach (SquadRack) that integrates seamlessly with existing datacenter infrastructure. - Team of industry veterans who have shipped over 100 million chips and generated $5B+ in prior revenue. ## Strategic Focus - Scaling production of Corsair to meet customer demand for agentic AI workloads (voice agents, coding tools, real-time inference). - Building a heterogeneous compute ecosystem where d-Matrix accelerators complement GPUs rather than replace them. - Expanding software stack (Aviator) and networking (JetStream) to deliver full-stack inference solutions. ## Why Work Here - **Culture**: “Round pegs in square holes” – builders, innovators, dreamers. Emphasis on humility, direct communication, and collaboration. - **Work model**: Remote & hybrid working model (global offices in Silicon Valley, Sydney, Bengaluru, Toronto, Belgrade). - **Benefits**: Competitive pay and equity, health care, flexible time-off, paid paternity leave, 401k, on-site fitness centers, free food/snacks, peer coaching & development, team-building activities. - **Engineering environment**: Work with world-leading engineers and researchers on cutting-edge AI hardware/software. Opportunity to shape the future of AI inference infrastructure. ## Sources 1. [d-matrix.ai – Homepage](https://www.d-matrix.ai/) 2. [d-matrix.ai – About / Leadership](https://www.d-matrix.ai/about/) 3. [d-matrix.ai – Careers](https://www.d-matrix.ai/careers/) 4. [d-matrix.ai – Corsair Production & AI Breakthrough Award](https://www.d-matrix.ai/announcements/d-matrix-corsair-ai-inference-platform-enters-full-production-to-meet-customer-demand/) 5. [CB Insights – d-Matrix Company Profile](https://www.cbinsights.com/company/d-matrix) 6. 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