---
title: 'Principal SOC Physical Verification & Integration Specialist at EnCharge AI'
canonical: 'https://feeny.ai/job/principal-soc-physical-verification-integration-specialist-encharge-ai-bengaluru-z28meksf9r5v'
type: 'job'
last_seen: '2026-09-12'
---

# Principal SOC Physical Verification & Integration Specialist at EnCharge AI

- **Company:** EnCharge AI
- **Location:** Bengaluru, India
- **Work type:** hybrid
- **Posted:** 2026-07-16
- **Last confirmed live:** 2026-09-12
- **Apply:** https://job-boards.greenhouse.io/enchargeai36/jobs/4322288009

## Job description

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

## The Role

We are seeking a thorough SOC Physical Verification & Integration Specialist to drive the physical assembly and signoff of our next-generation SOCs. In this role, you will own the physical integration strategy from the floorplan stage through to tapeout, ensuring seamless assembly of massive multi-hierarchical blocks. You will act as the critical bridge between block-level implementation, top-level integration, and final foundry signoff, ensuring that complex physical bottlenecks are resolved without compromising power, performance, or area (PPA).

## Key Responsibilities

- Top-Level Physical Integration: Drive the full-chip physical assembly of very large-scale SOCs (e.g., multi-billion transistor designs). Manage top-level floorplanning, bump planning, global power grid (PG) integration, and top-level clock/routing integration.
- Hierarchical Verification Methodology: Architect and deploy highly efficient, hierarchical physical verification (PV) flows. Define the boundary conditions, abstraction models, and interface rules required to assemble heavily partitioned, massive-scale designs.
- Signoff Execution & Debugging: Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using industry-standard tools (e.g., Siemens Calibre) at advanced process nodes (5nm, 3nm, or below).
- Cross-Functional Collaboration: Partner tightly with the Physical Design (PD) and Static Timing Analysis (STA) teams. Proactively resolve integration conflicts—such as top-level routing congestion or interface timing violations—ensuring that physical fixes do not disrupt timing closure.
- Design Rule Co-Optimization: Work directly with foundry partners to interpret complex design rules and waive or resolve edge-case violations specific to reticle-limit designs.
- Automation & Flow Development: Develop robust scripts and utilities to automate physical integration tasks, database merging, and PV result parsing to accelerate the tapeout cycle.

Required Qualifications

- Experience: 14 + years of hands-on experience in SOC physical design and physical verification, with a proven track record of taping out very large, complex SOCs (e.g., Datacenter, AI accelerators, or High-Performance Compute chips).

- Technical Domain Expertise: * Deep understanding of the entire RTL-to-GDSII flow, with expert-level knowledge of physical integration challenges in flat vs. hierarchical methodologies.

- Strong foundational understanding of Physical Design and Static Timing Analysis (STA) to effectively communicate with implementation teams and assess the timing impact of PV fixes.

- Tool Proficiency: * Mastery of top-level integration tools (Cadence Innovus).

- Expertise in physical verification suites (e.g., Siemens Calibre nmDRC/nLVS/PERC, Synopsys IC Validator).
- Familiarity with chip/package co-design and bump planning tools.

- Programming/Scripting: High proficiency in Tcl, Python, and/or Perl for EDA flow automation and database manipulation.

- Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

## Preferred Qualifications

- Experience with multi-die integration, 2.5D/3D packaging, or chiplet-based architectures.
- Previous experience leading tapeout operations for start-up or fast-paced advanced technology environments.
- Advanced knowledge of custom layout integration and mixed-signal IP drop-in

## About EnCharge AI

## Company Overview
- **One-liner**: EnCharge AI develops analog in-memory computing hardware and software to deliver high-efficiency, low-cost AI inference from edge devices to cloud data centers.
- **Entity Type**: Private (Series B – II stage)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2022
- **Founders**: Naveen Verma, Ph.D. (CEO) and Kailash Gopalakrishnan, Ph.D. (CTO)

## Core Business
- **Primary industry**: AI semiconductor hardware and embedded software products
- **Target customers**: B2B – enterprises deploying AI at scale, edge-device manufacturers, cloud service providers, and defense/industrial sectors
- **Mission**: Democratize advanced AI by enabling deployment beyond cloud infrastructure to local servers and mobile devices, while slashing costs and environmental impact

## Products & Services
- **Analog In-Memory Computing GPUs & Digital AI Accelerators**: Custom silicon (chiplets, ASICs) and standard-form-factor PCIe cards that perform AI inference using analog computation for orders-of-magnitude better energy efficiency and compute density.
- **Software Stack**: Seamless orchestration layer that supports on-device and cloud deployment, enabling model portability, quantization, and compiler optimizations across EnCharge’s hardware.
- **Edge-to-Cloud Platforms**: Integrated solutions for power-, space-, and cost-constrained environments, covering autonomous systems, smart devices, data center inference, and private on-premise AI.

## Market Standing
- **Valuation / Market Cap**: Not publicly disclosed
- **Key Metrics**: Annual Revenue ~$10M (LinkedIn estimate) | Total Funding $162.9M
- **Notable Investors & Partners**: Tiger Global Management (led $100M Series B, Mar 2025), Anzu Partners (led $21.7M Series A, Dec 2022), DARPA ($18.6M grant, Mar 2024), and others including corporate/institutional backers.
- **Growth Signals**: 
  - 58.6% YoY headcount growth (75 employees, as of mid-2025)
  - 39 active job openings spanning hardware, compiler, and AI architecture roles
  - 150+ patents granted, 300+ technical publications
  - Talent inflows from Intel, IBM, Cerebras, AMD, Meta, Microsoft

## Competitive Advantages
- **Analog In-Memory Computing Moa**t: A proprietary compute architecture that uses charge-domain analog circuits, validated silicon, and leverages existing semiconductor supply chains.
- **Record Efficiency**: Claims 20× higher TOPS/W, 9× higher compute density (TOPS/mm²), 10× lower total cost of ownership, and 100× lower CO₂ emissions compared to leading cloud/GPU alternatives.
- **Deep IP Portfolio**: 150+ granted patents and 300+ publications from 20+ years of foundational research by the founding team (Princeton, IBM, etc.).
- **End-to-End Solution**: Full-stack hardware and software (compiler, quantization, runtime) designed for seamless edge-to-cloud orchestration without vendor lock-in.

## Strategic Focus
- Scale production and customer deployments of their analog in-memory compute chips for high-volume edge and data center inference.
- Expand software ecosystem to support mainstream AI frameworks (PyTorch, TensorFlow, ONNX) and enable easy drop-in replacement for existing GPU-accelerated workloads.
- Deepen partnerships with defense (DARPA) and enterprise cloud providers, emphasizing data privacy, security, and sustainability.
- Double down on sustainability messaging (100× lower CO₂) to meet ESG mandates in enterprise AI procurement.

## Why Work Here
- **Mission-Driven Impact**: Opportunity to make AI accessible to the “99%” by dramatically reducing energy and cost barriers. Work is cited as a “once-in-a-lifetime” chance by leadership.
- **World-Class Team**: Colleagues include industry luminaries from Princeton, IBM, and top semiconductor houses; 57% of staff are in technical roles (engineering, research, compiler).
- **Culture of Collaboration & Innovation**: The careers page highlights integrity, growth, and collaborative problem-solving in a fast-paced startup environment.
- **Comprehensive Rewards**: Benefits package includes typical startup perks; equity likely offered given funding stage.
- **Work Policy**: Hybrid presence indicated by offices in Santa Clara, Canada, Germany, Norway, South Korea, and India. Remote flexibility likely for some roles.
- **Active Hiring**: 39 open positions across DFT, physical design, compiler engineering, and NPU architecture – strong signal of scaling and technical investment.

## Sources
1. [EnCharge AI Official Website](https://www.enchargeai.com/)
2. [EnCharge AI Careers Page](https://www.enchargeai.com/careers)
3. [EnCharge AI About Us (Leadership & Founders)](https://www.enchargeai.com/about-us)
4. [EnCharge AI LinkedIn Company Page](https://www.linkedin.com/company/encharge-ai)
5. [CB Insights Profile – EnCharge AI](https://www.cbinsights.com/company/encharge-ai)

## Other roles at EnCharge AI

- [Staff Physical Design Engineer](https://feeny.ai/job/staff-physical-design-engineer-encharge-ai-us-vva2w6eepdbk) — Us-, Canada
- [Technical Program Manager - Embedded Software](https://feeny.ai/job/technical-program-manager-embedded-software-encharge-ai-united-states-w18v49ve3s0r) — United States
- [Principal Solutions Engineer](https://feeny.ai/job/principal-solutions-engineer-encharge-ai-united-states-vgghgxj68g9h) — United States
- [Lead DFT Engineer](https://feeny.ai/job/lead-dft-engineer-encharge-ai-canada-united-states-q4ggksnf4q7g) — Canada / United States
- [Senior PD Engineer: Synthesis & STA](https://feeny.ai/job/senior-pd-engineer-synthesis-sta-encharge-ai-bengaluru-wfbtaq6984et) — Bengaluru, India
- [Senior Staff / Principal SOC Floorplan Lead](https://feeny.ai/job/senior-staff-principal-soc-floorplan-lead-encharge-ai-bengaluru-5rjzbdmx1e0r) — Bengaluru, India
- [Staff Engineer: STA Methodology & Sign-off Lead](https://feeny.ai/job/staff-engineer-sta-methodology-sign-off-lead-encharge-ai-bengaluru-dnr9280vbw00) — Bengaluru, India
- [Staff / Senior Staff CAD & Methodology Engineer (Digital Implementation & Signoff)](https://feeny.ai/job/staff-senior-staff-cad-methodology-engineer-digital-implementation-signoff-bbfjk21sk0rk) — Bengaluru, India
- [Research Engineer, AI Models](https://feeny.ai/job/research-engineer-ai-models-encharge-ai-germany-5kv1pnxdmybd) — Germany
- [Research Engineer, AI Models](https://feeny.ai/job/research-engineer-ai-models-encharge-ai-india-s35hk7vzfyr3) — India