--- title: 'RFIC Silicon Lead at Tacit' canonical: 'https://feeny.ai/job/rfic-silicon-lead-tacit-san-francisco-zdy00hqe0mnm' type: 'job' last_seen: '2026-09-09' --- # RFIC Silicon Lead at Tacit - **Company:** Tacit - **Location:** San Francisco, CA - **Compensation:** $180k–$230k - **Employment:** full-time - **Work type:** onsite - **Posted:** 2026-06-22 - **Last confirmed live:** 2026-09-09 - **Apply:** https://jobs.ashbyhq.com/tacit/d7eb5a2f-3e6b-44c3-8a46-327eeeb0d029 ## Job description ## About Tacit We are an early-stage, deep tech startup based in San Francisco, developing innovative hardware that rethinks human-computer interaction. We are backed by General Catalyst, Khosla Ventures, and Greylock Partners, with a founding team from Stanford, BrainGate, Oculus, and Tesla. While we can’t reveal too much just yet, our team is tackling cutting-edge engineering challenges to bring revolutionary products to life. ## ABOUT THE ROLE We are building CMOS RF systems at ultra low-power envelopes. We are looking for our first silicon hire: the person who will define the RF CMOS architecture, translate Tacit’s sensing and ML constraints into circuit reality, and set the technical foundation for everything that follows. This role starts hands-on. You will work at the transistor level, stand up the initial design environment, evaluate process options, simulate and design critical blocks, and drive early silicon decisions. But the most important responsibility is architectural judgment: determining what RF front-end, synthesizer, power-management, and duty-cycling approaches can actually close in CMOS at our target power envelopes. The rare skill we are looking for is not generic RFIC execution. It is the ability to reason across system architecture, low-power CMOS RF, frequency generation, sensing constraints, form factor, and product requirements — and to know when a proposed path will or will not work in silicon. As the program matures, you will help decide what stays internal and what is executed with external silicon partners. You may directly own blocks, technically direct contractors, or build the internal team. In all cases, the architecture-defining IP and technical judgment must live inside Tacit. ## WHAT YOU'LL DO - Define the RF CMOS architecture for an ultra-low-power, frequency-agile sensing front end - Translate system-level sensing, ML, and form-factor constraints into circuit-level requirements - Design and/or technically direct critical RF circuit blocks, including VCOs, PLLs, mixers, LNAs, buffers, passives, clocking, biasing, and power-management structures - Architect fast-settling frequency generation and hopping approaches suitable for aggressive duty-cycled operation - Drive power-reduction methodology across the RF system: duty-cycle co-design, supply gating, bias trimming, wake/sleep transients, and system-level power tradeoffs - Evaluate and recommend CMOS process options for a low-power wideband / frequency-agile SoC, including tradeoffs across 28nm, 22FDX, 55nm RF, and related nodes - Stand up and operate the early RFIC design environment, including Cadence Virtuoso, Spectre, ADE, EM simulation, Calibre, and PDK flows - Identify when an architecture will not close in silicon, and propose practical relaxations or alternatives - Own or technically direct implementation through DRC/LVS, tape-out, packaging, bring-up, measurement correlation, and iteration - Evaluate, select, and technically manage external silicon partners where appropriate, while keeping architecture-defining IP and technical judgment inside Tacit - Help build the future silicon team as the architecture, program, and company scale ## REQUIREMENTS - MS or PhD in electrical engineering, or equivalent experience - 10+ years in RFIC design, with substantial industry experience delivering silicon - Deep experience in low-power CMOS RF, synthesizers, radar, UWB, frequency-agile radios, or related sensing systems - Strong transistor-level design ability in Cadence Virtuoso, Spectre, and ADE - Expertise in synthesizer and RF front-end circuits, especially VCOs, PLLs, mixers, LNAs, buffers, passives, clocking, and biasing - Strong understanding of CMOS process tradeoffs, device behavior, stack selection, parasitics, layout effects, and RF process-node selection - Experience with EM simulation tools such as EMX, HFSS, Momentum, or equivalent - Track record taking RFIC blocks or systems from architecture through silicon validation - Ability to reason across architecture, circuits, layout, packaging, measurement, power, and product constraints - Ability to translate ambiguous system-level goals into concrete circuit and silicon tradeoffs - Strong communication skills and ability to lead technical decisions in a small, fast-moving team ## STRONG CANDIDATES MAY HAVE - Background in low-power radar, UWB, frequency synthesizers, or frequency-agile sensing front ends - Experience with fast-settling PLLs, wideband frequency generation, duty-cycled RF systems, or ultra-low-power sensing radios - Experience with 28nm, 22FDX, 55nm RF, or other RF-capable CMOS processes - Experience as a first or early silicon hire at a startup - Experience managing external design houses, foundries, packaging vendors, or semiconductor supply-chain partners - Experience with RF/analog/digital co-design and system-level power optimization - Experience building, hiring, or mentoring RFIC teams - Strategic mindset: engineering decisions framed in terms of business outcomes, product milestones, defensible IP, and time-to-market ## COMPENSATION RANGE $180,000 - $230,000/year plus meaningful equity package ## BENEFITS - Competitive equity package - Comprehensive medical, dental, and vision insurance - Company size: 30-50 people - Unlimited PTO - Visa sponsorship - 4% 401k matching ## About Tacit ## Company Overview - **One-liner**: An early-stage, stealth deep tech startup based in San Francisco, developing innovative hardware that rethinks human-computer interaction, with a focus on neurotechnology and Edge AI. - **Entity Type**: Private (Early Stage, Stealth) - **Headquarters**: San Francisco, California, United States - **Founded**: Not publicly available - **Founders**: Not publicly available (founding team includes alumni from Stanford, BrainGate, Oculus, and Tesla) ## Core Business - Primary industry/industries: Neurotechnology, Edge AI Hardware, Human-Computer Interaction - Target customers: B2B/B2C in consumer electronics, wearable tech, neurotech, and AR/VR sectors - Mission or purpose statement: To develop revolutionary hardware that redefines how humans interact with computers, leveraging deep tech innovations in neural interfaces and on-device artificial intelligence. ## Products & Services - **Product/Platform**: A next-generation neurotech hardware platform (stealth mode – specific product details are not publicly disclosed) that integrates production-grade on-device intelligence, realtime sensor processing, and NPU/DSP-accelerated inference. ## Market Standing - **Valuation/Market Cap**: Not disclosed (stealth startup) - **Key Metric**: Total Funding – Backed by top-tier venture firms (General Catalyst, Khosla Ventures, Greylock Partners) but specific funding amounts are not publicly available. - **Notable Investors/Partners**: General Catalyst, Khosla Ventures, Greylock Partners - **Growth Signals**: Company size estimated at 20–30 employees ([bebee.com](https://bebee.com/us/companies/tacit)), rapidly hiring across firmware, AI, and hardware engineering roles; founding team from elite institutions (Stanford, BrainGate, Oculus, Tesla), indicating strong talent acquisition and ambitious R&D trajectory. ## Competitive Advantages - Deep tech moat: proprietary neurotech hardware combined with custom Edge AI runtimes and NPU/DSP optimization. - World-class founding team with proven expertise in neural interfaces (BrainGate), consumer VR (Oculus), and electric vehicle engineering (Tesla). - Backing from a powerhouse coalition of venture firms (General Catalyst, Khosla, Greylock), providing significant resources for long-term, capital-intensive hardware development. - Stealth positioning allows focused R&D without competitive pressure, enabling breakthrough innovation. ## Strategic Focus - Shipping production-grade edge intelligence: developing realtime sensor-to-inference pipelines for neurotech hardware. - Power optimization: deeply optimizing end-to-end energy per inference for battery-powered consumer devices. - Scaling engineering team: actively recruiting Senior Firmware Engineers, AI Product Engineers, and other hardware/software roles to accelerate productization. - Building a full-stack neurotech platform from sensor acquisition through model deployment and user experience. ## Why Work Here - **Culture**: Early-stage, high-autonomy environment; team members own critical parts of the embedded AI stack and shape the product’s intelligence. - **Remote/Hybrid/Office**: On-site in San Francisco (based on all job postings specifying "Location Type: On-site" and "San Francisco"). - **Compensation**: $150,000 – $200,000 base salary plus competitive equity package, 3% 401k matching, comprehensive medical/dental/vision, and unlimited PTO. - **Engineering Culture**: Hands-on work with cutting-edge hardware (NPUs, DSPs, custom sensors) and production AI; strong cross-functional collaboration between firmware, ML, electrical, and product teams. - **Visa Sponsorship**: Offered for qualified candidates. - **Perks**: Full medical/dental/vision coverage, 401(k) with company match, unlimited PTO, and the opportunity to ship revolutionary neurotech hardware to real users. ## Sources 1. [Tacit Careers Page (Ashby)](https://jobs.ashbyhq.com/tacit/62712a3e-e5b8-4884-9450-aae4d2dfa45c) 2. [BeBee - Tacit Company Profile](https://bebee.com/us/companies/tacit) 3. [Jobright.ai - Tacit AI Product Engineer Posting](https://jobright.ai/jobs/info/6971dbb2b707bf728a4b654d) 4. [Indeed.com - Tacit Careers and Employment](https://www.indeed.com/cmp/Tacit) 5. [Tacit AI Official Website (Tacit AI)](https://tacitx.ai/about/) – *(Note: this domain appears distinct from tacit.ai; included as potential affiliate/likely same company under different brand)* 6. [Tacit Official Website](https://tacit.ai/) ## Other roles at Tacit - [Rapid Prototyping Engineer](https://feeny.ai/job/rapid-prototyping-engineer-tacit-san-francisco-c6r78rgdqcrg) — San Francisco, CA - [Frontend Product Engineer](https://feeny.ai/job/frontend-product-engineer-tacit-san-francisco-2t7b6qys1eg5) — San Francisco, CA - [Finance and Operations Lead](https://feeny.ai/job/finance-and-operations-lead-tacit-san-francisco-njjpatk3w9a3) — San Francisco, CA - [Technical Program Manager, Operations & Manufacturing](https://feeny.ai/job/technical-program-manager-operations-manufacturing-tacit-san-francisco-6bz0sxs5pxwn) — San Francisco, CA - [EE Systems Validation and Automation Engineer](https://feeny.ai/job/ee-systems-validation-and-automation-engineer-tacit-san-francisco-9cdw1f8w71cg) — San Francisco, CA - [RF Hardware Intern (Fall 2026)](https://feeny.ai/job/rf-hardware-intern-fall-2026-tacit-san-francisco-qxswc71mxb9g) — San Francisco, CA - [Machine Learning Scientist](https://feeny.ai/job/machine-learning-scientist-tacit-san-francisco-pt1w314e43ge) — San Francisco, CA - [Data Collection Technician](https://feeny.ai/job/data-collection-technician-tacit-san-francisco-z3hyxpf9r298) — San Francisco, CA - [Senior RF Validation Engineer](https://feeny.ai/job/senior-rf-validation-engineer-tacit-san-francisco-9xq9s0r3qxr1) — San Francisco, CA - [Senior Firmware Engineer, Edge AI / NPU Runtime](https://feeny.ai/job/senior-firmware-engineer-edge-ai-npu-runtime-tacit-san-francisco-pe289s2hzda4) — San Francisco, CA