---
title: 'RTL Design Engineer at Delos Data Inc'
canonical: 'https://feeny.ai/job/rtl-design-engineer-delos-data-inc-palo-alto-646y3xe9876r'
type: 'job'
last_seen: '2026-11-03'
---

# RTL Design Engineer at Delos Data Inc

- **Company:** Delos Data Inc
- **Location:** Palo Alto, CA
- **Employment:** full-time
- **Work type:** remote
- **Posted:** 2026-10-20
- **Last confirmed live:** 2026-11-03
- **Apply:** https://jobs.ashbyhq.com/delos-data/d89477e0-82b6-4abb-aefa-a5ea95d264a9

## Job description

Senior RTL Design Engineer Who we are: We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need: An experienced Senior RTL Design Engineer responsible for designing, implementing, and delivering high-quality RTL for complex digital systems. This role focuses on translating architectural specifications into scalable microarchitectures and production-ready RTL, with strong attention to performance, power, and area. The ideal candidate has deep hands-on experience with Verilog/SystemVerilog, strong digital design fundamentals, and experience working across the full design lifecycle in collaboration with architecture, verification, and physical design teams. Key Responsibilities:

- Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog
- Translate architectural specifications into clean, efficient, and scalable microarchitectures
- Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure
- Develop high-quality, reusable RTL with strong coding standards and documentation
- Perform linting, CDC analysis, and ensure synthesis readiness of designs
- Support integration and debug of RTL in simulation and early silicon environments
- Participate in design reviews and provide technical input on architecture and implementation tradeoffs
- Work with verification teams to ensure comprehensive functional coverage
- Assist in timing closure and support backend teams as needed
- Contribute to continuous improvement of design methodologies, flows, and tools Required Skills and Qualifications:
- · Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
- 5+ years of experience in RTL design
- Strong hands-on experience with Verilog/SystemVerilog
- Solid understanding of synchronous digital design and microarchitecture principles
- Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE)
- Familiarity with synthesis, timing, and physical design constraints
- Strong analytical and problem-solving skills
- Clear written and verbal communication skills for cross-functional collaboration
- High attention to detail and ability to deliver high-quality design outcomes
- Ability to work independently and manage tasks to completion, including AI-assisted workflows

Desired Skills:

- Experience designing high-performance systems (e.g., AI/ML accelerators, networking, or SoCs)
- Familiarity with low-power design techniques (clock gating, power gating)
- Exposure to DFT concepts and design-for-test considerations
- Experience with scripting (Python, Tcl, or similar)
- Experience working in advanced semiconductor process nodes
- Experience using AI coding agents (e.g., Claude Code, Cursor, Copilot) in RTL workflows such a implementation, debug, and timing closure, with the rigor to verify AI-generated output
- Interest in turning design experience into reusable AI agent guidance, such as RTL coding patterns, timing-closure playbooks, or review checklists

Compensation: Target base salary for this role is $160,000 – $240,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location. We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics. Agency Note: We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.

## #LI-EW1

## About Delos Data Inc

## Company Overview
- **One-liner**: Delos Data builds a new interconnect architecture and server design purpose-built for AI inference, enabling faster, more scalable inference by eliminating network bottlenecks.
- **Entity Type**: Private (Stealth/Seed stage)
- **Headquarters**: Palo Alto, California, USA
- **Founded**: 2025
- **Founders**: Ed Doe (CEO & Co-Founder), Dan Daly (CTO & Co-Founder)

## Core Business
- **Primary Industry**: Semiconductor Manufacturing / AI Infrastructure
- **Target Customers**: Hyperscalers, AI infrastructure builders, and enterprises scaling AI inference workloads (B2B)
- **Mission/Purpose**: To deliver the world's most capable and responsive intelligence by building an interconnect purpose-built for AI inference, not borrowed from HPC, cloud, or training.

## Products & Services
- **Nonstop AI™**: A new cluster architecture and server design that accelerates AI inference through cabled scale-up. It reduces GPU idle time caused by data center interconnect bottlenecks and is designed to flexibly scale to thousands of GPUs, CPUs, and accelerators.
- **Delos Server**: Brings scale-up IO to the network fabric, enabling larger scale-up domains for inference.
- **Delos Mosaic™**: Software providing fine-grained visibility into the scale-up domain, allowing for real-time inference bottleneck detection and AI workload tuning.

## Market Standing
- **Valuation**: Not publicly disclosed (Private, early-stage company)
- **Key Metric**: Total funding not publicly disclosed; company is in early access deployment with select customers.
- **Notable Investors/Partners**: Not publicly disclosed; company exhibited at NVIDIA GTC 2026 (Booth 150) and will demonstrate at Computex 2026 (Booth J1328).
- **Growth Signals**: 
  - Founded in 2025, already has 3 employees with 25% monthly headcount growth.
  - 7 active job postings as of mid-2026.
  - Announced Nonstop AI™ architecture in May 2026 with early access deployments.
  - Exhibited at major industry events (NVIDIA GTC 2026, Computex 2026).
  - Website traffic growing 39.4% month-over-month.

## Competitive Advantages
- **Purpose-built for inference**: Unlike competitors who borrow interconnects from HPC, cloud, or training, Delos Data builds an interconnect specifically designed for AI inference workloads.
- **Cabled scale-up architecture**: Enables flexible scaling to thousands of GPUs, CPUs, and accelerators, reducing GPU idle time caused by network bottlenecks.
- **Full-stack approach**: Combines hardware (Delos Server), software (Delos Mosaic™), and silicon expertise to deliver a unified system-level solution.
- **Ecosystem compatibility**: Built to work within today's GPU and accelerator ecosystems, making adoption easier for hyperscalers and enterprises.
- **Founding team pedigree**: CTO Dan Daly and CEO Ed Doe bring deep expertise from leading semiconductor and AI companies.

## Strategic Focus
- **Product launch and market entry**: Currently in early access with select customers, with broader availability planned for Q4 2026.
- **Scaling the team**: Actively hiring across engineering (system software, DFT, verification, SDET), advanced packaging, and people operations roles.
- **Building the brand**: Establishing presence at major industry events (NVIDIA GTC, Computex) to build credibility and attract top talent.
- **Targeting hyperscalers and AI infrastructure builders**: The primary customer base for the Nonstop AI™ architecture.

## Why Work Here
- **Mission-driven work**: Opportunity to build foundational infrastructure for the next generation of AI, working on a problem the founders describe as "the next leap in AI performance."
- **Early-stage impact**: Join a company founded in 2025 with only 3 employees, offering significant ownership and influence over product and culture.
- **Hybrid/Remote flexibility**: Roles are listed as both remote and hybrid (Palo Alto, CA and Montréal, QC, CAN), with a "Remote Workspace" designation for many positions.
- **Founding team**: Work directly under experienced leadership (CTO Dan Daly, CEO Ed Doe) with deep expertise in semiconductors and AI.
- **Cutting-edge tech stack**: Work with Kubernetes, PyTorch, CUDA, SystemVerilog, Python, Terraform, and more across hardware and software domains.
- **High-growth trajectory**: 25% monthly headcount growth, active hiring across 7+ roles, and strong momentum from major industry events.

## Sources
1. [delosdata.com](https://delosdata.com/)
2. [builtin.com](https://builtin.com/company/delos-data)
3. [linkedin.com](https://www.linkedin.com/company/delosdata)
4. [delosdata.com/press](https://www.delosdata.com/press/faster-ai-inference-enabled-by-1000x-higher-scale-with-delos-data-nonstop-ai)
5. [opencorpdata.com](https://opencorpdata.com/us-va/11860584)

## Other roles at Delos Data Inc

- [Architect](https://feeny.ai/job/architect-delos-data-inc-palo-alto-50f77qzj5ewp) — Palo Alto, CA
- [AI Infrastructure Engineer](https://feeny.ai/job/ai-infrastructure-engineer-delos-data-inc-cambridge-pq4kk9efmrc9) — Cambridge, MA
- [Verification Engineer](https://feeny.ai/job/verification-engineer-delos-data-inc-palo-alto-rg1anvpfs5px) — Palo Alto, CA
- [System Software Engineer - AI](https://feeny.ai/job/system-software-engineer-ai-delos-data-inc-montreal-rpy5eqj29k80) — Montréal, Canada
- [Software Development Engineer in Test - AI](https://feeny.ai/job/software-development-engineer-in-test-ai-delos-data-inc-montreal-k0g110pt6p2h) — Montréal, Canada
- [Forward Deployed Engineer](https://feeny.ai/job/forward-deployed-engineer-delos-data-inc-cambridge-ym3ff1640191) — Cambridge, MA
- [Senior Electrical Engineer, Server Hardware 資深伺服器硬體工程師](https://feeny.ai/job/senior-electrical-engineer-server-hardware-delos-data-inc-taiwan-sj99t7zk0r06) — Taiwan
- [Principal Package Engineer](https://feeny.ai/job/principal-package-engineer-delos-data-inc-palo-alto-w5bhyzdw878e) — Palo Alto, CA
- [DFT Engineer](https://feeny.ai/job/dft-engineer-delos-data-inc-palo-alto-2v1vtamcm885) — Palo Alto, CA
- [SerDes Validation Leader](https://feeny.ai/job/serdes-validation-leader-delos-data-inc-palo-alto-cgr5a14pkbw8) — Palo Alto, CA