---
title: 'RTL Design Lead/IC Front-End Architect/Datapath Lead at Lumilens'
canonical: 'https://feeny.ai/job/rtl-design-lead-ic-front-end-architect-datapath-lead-lumilens-bengaluru-55p6s7qg41qp'
type: 'job'
last_seen: '2026-09-14'
---

# RTL Design Lead/IC Front-End Architect/Datapath Lead at Lumilens

- **Company:** Lumilens
- **Location:** Bengaluru, India
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-06-24
- **Last confirmed live:** 2026-09-14
- **Apply:** https://jobs.ashbyhq.com/lumilens/7aa98243-a799-4d2c-8c05-300726cc7170

## Job description

## About Lumilens

At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient. We’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry. This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. The market is moving fast, and we’re moving faster. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow. If you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started.

## About the Role

You own verification end to end for a first-of-its-kind chiplet. As a founding hire you define the methodology before there's RTL to verify — this role is on the critical path, and getting the coverage strategy and regression infrastructure right early is the single biggest schedule lever we have. About the role. You define the digital front-end micro-architecture — the spec the design team implements — and personally own the high-speed datapath that moves data between UCIe and the optical front end. This is the architectural center of the chip: the datapath, the UCIe streaming interface, in-house IP, and the interface to the optical engine all converge in your blocks. As a founding hire you set the partitioning, interfaces, and coding/CDC standards the whole front end follows.

## What you'll own

- Front-end micro-architecture and block partitioning; the architecture spec the RTL team builds to.
- Front-end design methodology and quality: RTL coding standards, lint, CDC/RDC signoff, and clean-RTL policy across the team.
- The high-speed datapath: per-lane alignment/deskew/mux, the UCIe streaming /RDI adapter, elastic FIFOs, and custom logic.
- Transport/link framing/mapping and the adaptation logic.
- Timing- and floorplan-aware micro-architecture: pipelining, retiming, and partitioning for physical closure at multi-hundred-Gbps (with the backend team).
- Clocking, reset, and low-power architecture — clock/reset domains, gating strategy, and UPF power intent.
- Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA) coverage that designers own before handoff to DV.
- Architectural DFT and debug provisioning — scan-friendly structure and on-die observability/controllability for a die you can't probe (with the DFT and DV leads).
- IP integration and interface/register conventions; parameterization for configurability across lane counts/configurations.
- Architectural trade-offs with the modelling lead (latency, buffering, datapath sampling/observability) and the DV lead (verifiability and debug).
- Lead, grow, and mentor the front-end design team as the group scales (datapath, interfaces, integration).

Required

- 10+ years digital design / micro-architecture, with lead ownership of a high-throughput datapath or SerDes-adjacent SoC.
- Experience designing the datapath of a network switch/NIC card or memory controller at a major XPU / fabric vendor (or a comparable high-throughput, high-reliability datapath).
- Solid understanding of scale-up vs. scale-out interconnect architectures and their bandwidth/latency trade-offs.
- Strong SystemVerilog RTL and timing-aware micro-architecture at multi-hundred-Gbps aggregate rates; CDC discipline.
- Working command of UCIe/PCIe/CXL datapath concepts and high-speed lane alignment/deskew.
- Proven ownership of front-end design methodology — lint/CDC/RDC signoff, clocking/reset architecture, and design-for-test and physical-closure collaboration.
- Track record translating system requirements into an implementable, verifiable architecture spec.

## Preferred

- UCIe (or PCIe/CXL/CHI) interface architecture; die-to-die / chiplet experience.
- FEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping.
- Optical transceiver, CPO, or linear-drive optics background; advanced-node (N5/N3/N2) design experience.

## What We Offer

- Competitive salary commensurate with experience
- Comprehensive benefits package including health, dental, and vision
- Professional development opportunities and certification support
- Access to cutting-edge technology and cloud platforms
- Collaborative work environment with cross-functional teams

Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender identity, sexual orientation, veteran status, disability, or any other legally protected status.

## About Lumilens

## Company Overview
- **One-liner**: Lumilens designs and manufactures next-generation photonic interconnects to massively scale AI compute infrastructure.
- **Entity Type**: Private (Series B – led by Accton Technology; prior Series A of $30M from Mayfield and Spark Capital)
- **Headquarters**: San Jose, California, USA
- **Founded**: 2024
- **Founders**: Ankur Singla (CEO), Samuel Liu (VP Products), Ritesh Kapahi (VP/GM India), Dave Friedman (VP Operations)

## Core Business
- **Primary industry**: Photonics / optical interconnects for AI data centers
- **Target customers**: Large-scale AI providers and hyperscale data center operators (B2B, Enterprise)
- **Mission**: “To rapidly innovate in photonics and connectivity architectures to enable the massive scaling of compute infrastructure required to deliver the full potential of AI.”

## Products & Services
- **Photonic Interconnects (Scale-Out & Scale-Up)**: High-density, low-latency optical links that enable cluster-to-cluster and direct GPU-to-GPU connectivity. Supports 100x higher quantity of GPU direct connections than legacy approaches.
  - *Type*: Hardware (silicon photonics modules) + integrated manufacturing
- **Automated Manufacturing Platform**: End-to-end custom robotics and AI-optimized production processes to maximize yield, quality, and supply-chain flexibility.
  - *Type*: Service / Manufacturing capability (in-house)

## Market Standing
- **Valuation/Market Cap**: Not publicly available
- **Key Metric**: Total funding – $30M Series A (June 2024); Series B led by Accton Technology (amount undisclosed)
- **Notable Investors/Partners**: Mayfield, Spark Capital, Accton Technology
- **Growth Signals**:
  - Headcount grew 287% YoY (54 employees as of mid-2025) [linkedin.com]
  - Operations in 8 countries: USA, India, Thailand, Poland, Singapore, Czechia, South Korea, Malaysia
  - 48 active job postings (+23.1% monthly growth) [linkedin.com]
  - Leadership team with deep photonics/networking experience from Cisco, Juniper, Meta, Lumentum, Coherent

## Competitive Advantages
- **In-house silicon photonics development** – full control over design and supply chain
- **Systems-level expertise** – can partner on both scale-out and scale-up architectures
- **Manufacturing automation** – robotics + AI processes enable faster innovation, higher quality, and predictable deployment
- **Standards-based interconnects** – easy deployment into existing infrastructure
- **Manufacturing anywhere** – supply-chain continuity and scalable manufacturing

## Strategic Focus
- Enable massive scaling of AI infrastructure by overcoming electrical/copper limitations with advanced photonics
- Disaggregate GPUs to mitigate power and density challenges in data centers
- Expand manufacturing capacity globally and continue to automate production
- Align product roadmap with industry standards to accelerate adoption

## Why Work Here
- **Culture**: Fast-paced startup environment with deep technical expertise; mission-driven focus on enabling the future of AI
- **Work policy**: In-office (HQ San Jose, CA with Bengaluru, India as major hub) [builtin.com]
- **Perks**: Opportunity to work on cutting-edge photonics, robotics, and AI manufacturing; direct impact on world’s largest AI infrastructure
- **Engineering culture**: Heavy emphasis on silicon photonics, hardware design, robotics automation, and system-level architecture. Teams are led by veterans from Cisco, Juniper, Meta, Lumentum, Coherent.

## Sources
1. [lumilens.com](https://lumilens.com/) – Company overview, mission, leadership, products
2. [lumilens.com/company](https://lumilens.com/company) – Vision, investors, leadership team
3. [builtin.com](https://builtin.com/company/lumilens) – Career page, employee count, year founded, office policy
4. [linkedin.com](https://www.linkedin.com/company/lumilens) – Headcount, funding details, geographic/department breakdown, job trends, talent sources
5. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/lumilens) – Current job openings (48 listings)

## Other roles at Lumilens

- [Senior/Staff Process Engineer (Flip Chip)](https://feeny.ai/job/senior-staff-process-engineer-flip-chip-lumilens-singapore-64nme1rs25n7) — Singapore
- [Senior/Staff Process Engineer (Wafer Dicing & Back-grind)](https://feeny.ai/job/senior-staff-process-engineer-wafer-dicing-back-grind-lumilens-singapore-x7ndepxkpsq1) — Singapore
- [Process Technician](https://feeny.ai/job/process-technician-lumilens-chon-buri-09kznv0jezc2) — Chon Buri, Thailand
- [Active Alignment & NPI Process Development Engineer](https://feeny.ai/job/active-alignment-npi-process-development-engineer-lumilens-singapore-32wpsa2ww70y) — Singapore
- [Staff Engineer (Foundry Operations)](https://feeny.ai/job/staff-engineer-foundry-operations-lumilens-singapore-2b6mww54qfxg) — Singapore
- [Capital Equipment Sourcing & Procurement Director](https://feeny.ai/job/capital-equipment-sourcing-procurement-director-lumilens-singapore-wvczymcygsw4) — Singapore
- [Staff Wafer-Level Testing Equipment Engineer](https://feeny.ai/job/staff-wafer-level-testing-equipment-engineer-lumilens-singapore-2p0ya27rda60) — Singapore
- [Sourcing Manager (Foundry & OSAT)](https://feeny.ai/job/sourcing-manager-foundry-osat-lumilens-singapore-26re9q580khj) — Singapore
- [Senior/ Staff NPI Wafer Bumping/Fan-Out Process Engineer](https://feeny.ai/job/senior-staff-npi-wafer-bumping-fan-out-process-engineer-lumilens-singapore-ma0tx35az5eq) — Singapore
- [Staff Wafer-level Testing Engineer (Operations & Process)](https://feeny.ai/job/staff-wafer-level-testing-engineer-operations-process-lumilens-singapore-cvp2fdz9w4qr) — Singapore