---
title: 'RTL Lead at Normal Computing Corporation'
canonical: 'https://feeny.ai/job/rtl-lead-normal-computing-corporation-mountain-view-1hjck5sazc2b'
type: 'job'
last_seen: '2026-11-05'
---

# RTL Lead at Normal Computing Corporation

- **Company:** Normal Computing Corporation
- **Location:** Mountain View, CA
- **Employment:** full-time
- **Work type:** hybrid
- **Posted:** 2026-10-29
- **Last confirmed live:** 2026-11-05
- **Apply:** https://jobs.ashbyhq.com/normalcomputing/00c56877-13a9-4024-a0cf-ba775ef45ca7

## Job description

Normal Computing | Build with Us Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London.

## The Role

Hybrid: 3 days a week in the office, in Mountain View, New York or London. As a Lead RTL Design Engineer at Normal, you will lead and own the design of the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence. You will lead and own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely with physical design to make sure the design meets area and timing constraints. As a Lead, you will help with hiring, create and refine the design methodology, organize the design team around schedule and track progress. Because Normal's chips are not standard accelerators, the Lead RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it. This role requires a seasoned engineer with a track record of driving key initiatives, energizing the RTL team, and fostering cross-functional alignment across architecture, verification, and physical design. The ideal candidate has successfully led silicon through tapeout sign-off, played an active role in RTL implementation and design closure, and thrives in a dynamic setting where system specifications evolve alongside architectural and design development.

## What You Will Own

- Team Leadership: Organize and set the standard and high expectations for the RTL design team. Foster a collaborative and execution focused environment.
- RTL Design: Create and enforce RTL coding standards. Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
- Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.
- Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.
- Physical Design Collaboration: Collaborate with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT.
- Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.
- Tapeout & Bring-up: Support tapeout preparation, create tapeout criteria, signoff on tapeout readiness, and post-silicon bring-up as needed.

What Makes You a Great Fit

- Experience leading an RTL design team through multiple tapeouts. This includes block and toplevel work.
- Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route for multiple blocks and design.
- Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
- Strong debugging instincts across simulation, waveforms, and formal counterexamples
- Ability to work directly with architects and physical designers

Bonus Points

- Experience at an AI chip company where design and verification were tightly coupled
- Experience with multiple interface architectures, for example PCIe, Ethernet, and memory devices.
- Familiarity with FPGAs
- Experience with AI-assisted RTL or EDA tooling in your design workflow
- Exposure to physical design constraints, floorplanning, or timing-driven RTL development

## Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our [Applicant Privacy Notice](https://normalcomputing.com/applicant-privacy-notice).

## About Normal Computing Corporation

## Company Overview
- **One-liner**: Normal Computing builds AI-accelerated EDA software and physics-based ASICs to enable ultra-efficient hardware for the AI era.
- **Entity Type**: Private (Series B; total funding $92.5M)
- **Headquarters**: New York, New York, USA
- **Founded**: 2022
- **Founders**: Faris Sbahi (CEO), Matthias Tan (Co-Founder), and team of former Google Brain/Google X engineers and scientists

## Core Business
- Primary industry: Semiconductor design (EDA) and custom silicon (ASICs), powered by AI and probabilistic computing.
- Target customers: Large semiconductor design and manufacturing institutions (B2B, enterprise).
- Mission: "Rewriting AI foundations to advance the frontier of reasoning and reliability in the physical world" and enabling a virtuous cycle of self-improving AI hardware.

## Products & Services
- **[Normal EDA](https://normalcomputing.com/)**: An AI-driven electronic design automation platform that understands design intent from specification documents, generates hierarchical test plans with traceability, creates SystemVerilog stimulus, runs simulations, and tracks coverage. It continuously learns from team feedback to accelerate verification for complex chip designs.
- **[Normal ASICs](https://normalcomputing.com/)**: Physics-based custom ASICs that relax traditional computing assumptions (stochastic, stateful, asynchronous) to unlock orders-of-magnitude more efficient compute. Designed to converge hardware with the physical dynamics of AI models.

## Market Standing
- **Valuation/Market Cap**: Not publicly disclosed.
- **Key Metric**: **Total Funding** – $92.5M across multiple rounds (Seed, Venture, Grant, Series B). Notable recent round: $50M led by **Samsung Catalyst** in March 2026 [normalcomputing.com](https://normalcomputing.com/).
- **Notable Investors**: Samsung Catalyst Fund, Intel Ignite, First Spark Ventures, Celesta Capital, ARIA. Also partners with Fraunhofer IESE (DRAMBench benchmark).
- **Growth Signals**: Headcount grew **196.3% YoY** to 54 employees; operates across 6 countries (US, UK, Denmark, Switzerland, India, Canada); actively building open-source tools (e.g., a Verilog simulator built with AI: 580K lines in 43 days).

## Competitive Advantages
- **Physics-First Approach**: Unlike traditional digital logic, Normal’s ASICs embrace stochastic, stateful, and asynchronous computing – aligning hardware with the physics of AI models for dramatic efficiency gains.
- **Full-Stack Co-Design**: The combination of AI-native EDA tools and custom silicon creates a closed loop where software and hardware are co-optimized, shortening time-to-market and enabling workload-specific ASICs.
- **Deep AI Heritage**: Founders and team hail from Google Brain and Google X, bringing deep expertise in probabilistic ML, quantum AI, and physical-world reasoning.

## Strategic Focus
- **Scaling EDA Adoption**: Expanding Normal EDA’s use among top semiconductor companies to "make chip design look more like software".
- **AI Hardware Energy Crisis**: Tackling soaring power demands of AI by delivering ultra-efficient ASICs that can be produced for every workload.
- **Open-Source & Research**: Building community trust through open benchmarks (DRAMBench) and tools (CIRCT-based verification), while advancing formal methods and AI-driven simulation.

## Why Work Here
- **Hybrid Workspace**: Flexible in-office collaboration at offices in **New York (Flatiron HQ)**, **San Francisco**, **London**, and **Copenhagen**. In-person collaboration is valued but with flexibility; free lunch, snacks, and beverages in office.
- **Lean, High-Impact Team**: Small team (54 employees) where every member drives significant impact, works directly with customers, and owns meaningful parts of the product.
- **Interdisciplinary Challenges**: Work spans AI, probabilistic software, hardware, physics, and full-stack engineering – ideal for curious, passionate problem-solvers.
- **Strong Growth Trajectory**: Rapid headcount growth (+196% YoY), recent $50M Series B, and partnerships with industry giants signal a well-funded, high-potential startup.

## Sources
1. [normalcomputing.com](https://normalcomputing.com/)
2. [normalcomputing.com/about](https://normalcomputing.com/about)
3. [linkedin.com/company/normal-computing-corporation](https://www.linkedin.com/company/normal-computing-corporation)
4. [builtin.com/company/normal-computing](https://builtin.com/company/normal-computing)
5. [jobs.ashbyhq.com/normalcomputing](https://jobs.ashbyhq.com/normalcomputing)

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