--- title: 'Senior Analog/RF Layout Engineer at Phizenix' canonical: 'https://feeny.ai/job/senior-analog-rf-layout-engineer-phizenix-bengaluru-gen055rfqf07' type: 'job' last_seen: '2026-09-10' --- # Senior Analog/RF Layout Engineer at Phizenix - **Company:** Phizenix - **Location:** Bengaluru, India - **Work type:** hybrid - **Posted:** 2026-07-20 - **Last confirmed live:** 2026-09-10 - **Apply:** https://job-boards.greenhouse.io/phizenix/jobs/5364832008 ## Job description ## Role Overview As a Senior Analog/RF Layout Engineer, you will contribute to all phases of physical design—from concept through tapeout—focused on block-level layout with support for top-level integration. Working with circuit designers, packaging, process, and product teams, you will build robust, manufacturable layouts that meet performance, reliability, area, and schedule goals, helping deliver high-speed electrical IP such as SerDes, PAM4 interfaces, D2D PHY, and clocking subsystems. ## What You Will Do - Drive layout and physical implementation of analog/mixed-signal circuits, high-speed interfaces (SerDes, PAM4), and supporting digital blocks. - Own block-level floorplanning, placement, routing, and integration for complex mixed-signal ICs. - Translate schematics and performance targets into optimized layouts—tuned for matching, parasitics, signal/power integrity, thermal behavior, yield, and manufacturability. - Ensure compliance with all foundry rules (DRC, LVS, ERC, density, EM/IR, reliability). - Support top-level assembly across analog, digital, and high-speed domains (SerDes, PAM4 paths, clocking, control logic). - Review post-layout extraction and support simulation closure, applying best practices for symmetry, shielding, and isolation. - Partner with packaging and product teams on bump planning, pad ring, ESD structures, and package integration. - Drive layout-related issues affecting performance, yield, or production readiness; contribute to reviews on feasibility, tradeoffs, and tapeout risk. - Support tapeout readiness (database checks, signoff), CAD flow/automation improvements, mentoring of junior engineers, and post-silicon debug of layout issues. Tools & EDA Expertise Strong hands-on command of the Cadence Virtuoso custom-design platform is essential—deep tool fluency keeps the learning curve short. We expect working expertise across the following (or close equivalents): - Virtuoso Layout Suite (XL / GXL) for connectivity- and constraint-driven custom layout, including Modgen and structured/array generation for matched devices. - EM simulators like EMX, HFSS, Lorentz Peakview, etc. - Virtuoso Electrically Aware Design (EAD) for in-design EM/IR and parasitic-aware high-speed layout. - Quantus QRC extraction; physical verification with Cadence Pegasus (or Assura) and/or Siemens Calibre — DRC, LVS, ERC, density. - Voltus-Fi / Virtuoso Power for EM/IR signoff; SKILL scripting plus Python / Perl / TCL for automation. ## Who You Are - Bachelor's in Electrical Engineering or related (Master's a plus), with 6–8 years in custom IC layout for analog, mixed-signal, and high-speed designs. - Strong foundation in matching, symmetry, shielding, parasitic control, thermal management, and signal integrity, with interest in growing into layout leadership. - Command of device-level techniques (common-centroid, interdigitation, guard rings, isolation structures). - Solid grasp of DRC, LVS, ERC, parasitic extraction, EM/IR analysis, and physical signoff flows; comfortable working in Linux. - Familiarity with ASIC/SoC tapeout processes and layout automation scripting is preferred. - Strong analytical, problem-solving, communication, and teamwork skills, effective across geographically distributed teams. ## Minimum Qualifications - Bachelor's or Master's in Electrical Engineering or equivalent field. - 3+ years of layout design experience in analog, mixed-signal, or high-speed IC development. - Hands-on experience taking block-level layout through tapeout. - Strong custom-layout, physical-verification, and parasitic-aware implementation skills with Cadence Virtuoso or comparable tools. ## About Phizenix ## Company Overview - **One-liner**: Phizenix provides workforce solutions for the AI era, including top tech talent placement, AI strategy & development, and AI workforce training. - **Entity Type**: Private (Pre-Seed / Bootstrapped – no public funding rounds disclosed) - **Headquarters**: Livermore, California, United States - **Founded**: 2025 - **Founders**: Khursheed Irani ## Core Business - **Primary industry**: IT Services and IT Consulting, AI Consulting, Workforce Staffing - **Target customers**: B2B – businesses seeking AI transformation, technical talent, and AI upskilling (mid-market to enterprise) - **Mission or purpose statement**: “We’re a team of tech founders, operators, and builders on a mission to help businesses thrive in an AI-native world. We believe AI should empower people, not replace them.” ## Products & Services - **[Talent Staffing]**: Executive recruiting, permanent hire, contract staffing and management for technical roles (e.g., AI/ML engineers, DevOps, firmware engineers). - **[AI Strategy & Development]**: Consulting to discover automation opportunities, design AI solutions, and build production AI systems. - **[AI Workforce Training]**: Live workshops and online certification programs to increase teams’ AI skills. ## Market Standing - **Valuation/Market Cap**: Not publicly available (private company, no funding rounds disclosed) - **Key Metric**: Not disclosed (revenue not public). Employees: 12 as of early 2026. - **Notable Investors/Partners**: No named investors; leadership includes Khursheed Irani (CEO), Raashid Mehasanewala (Head of Solutions), Jumana Ghadiali (VP Operations), Sanjay Dayal (Senior Technology Advisor), Aziz Ghadiali (Head of AI and Marketing). - **Growth Signals**: Headcount growth of +7.7% monthly (LinkedIn estimate); active job postings on Greenhouse (3 open roles as of 2026); LinkedIn follower count 3,587 with +3.9% monthly growth. ## Competitive Advantages - **AI-native focus**: Entire business model centered on AI transformation, not a general staffing firm. - **Silicon Valley presence**: HQ in Livermore, CA, with additional presence in India and Canada, allowing access to diverse talent pools. - **Experienced leadership team**: Founders and VPs bring 20+ years of combined experience in tech, operations, and AI. ## Strategic Focus - **Current priorities**: Expand AI consulting engagements, scale talent staffing pipeline, and grow the training certification arm. Emphasis on “AI-native future of work” – helping companies integrate AI alongside human teams rather than replacing them. ## Why Work Here - **Culture**: Small, mission-driven team focused on AI empowerment. Emphasis on “AI should empower people, not replace them.” - **Remote/Hybrid/Office**: Many roles are remote; some are hybrid in San Francisco/Bay Area (e.g., Director of Engineering – Shopify & ERP). Offices in Livermore, CA and Bengaluru, India. - **Notable perks/engineering culture**: Opportunity to work at the intersection of AI and business transformation; hands-on involvement in building AI solutions for clients; growth potential in a young, rapidly expanding company. ## Sources 1. [phizenix.com](https://www.phizenix.com/) 2. [phizenix.com/careers](https://www.phizenix.com/careers) 3. [phizenix.com/about](https://www.phizenix.com/about) 4. [LinkedIn/Phizenix](https://www.linkedin.com/company/phizenix) 5. [Greenhouse/Phizenix](https://job-boards.greenhouse.io/phizenix/jobs/5197144008) ## Other roles at Phizenix - [Sr. Staff Backend Engineer](https://feeny.ai/job/sr-staff-backend-engineer-phizenix-hyderabad-psrdjq79ha1t) — Hyderabad, India - [LLM / Agentic Evaluation Rig Engineer](https://feeny.ai/job/llm-agentic-evaluation-rig-engineer-phizenix-hyderabad-x3nrtpps5f6d) — Hyderabad, India - [QA Automation Engineer](https://feeny.ai/job/qa-automation-engineer-phizenix-hyderabad-emn3ryp3sk2z) — Hyderabad, India - [Product Manager- Workflows](https://feeny.ai/job/product-manager-workflows-phizenix-remote-kp0tpcrhcbpd) - [Senior Analog & Mixed-Signal IC Designer](https://feeny.ai/job/senior-analog-mixed-signal-ic-designer-phizenix-santa-clara-22hs598ryxs0) — Santa Clara, CA / Irvine, CA - [ASIC Physical Design Engineer](https://feeny.ai/job/asic-physical-design-engineer-phizenix-bengaluru-sd4fja8bp25t) — Bengaluru, India - [Digital Design Lead](https://feeny.ai/job/digital-design-lead-phizenix-santa-clara-gb92mzn0r7vw) — Santa Clara, CA - [Senior Analog & Mixed-Signal IC Designer](https://feeny.ai/job/senior-analog-mixed-signal-ic-designer-phizenix-bengaluru-gzxnw70c7jwj) — Bengaluru, India - [Analog & Mixed-Signal IC Design Lead Engineer](https://feeny.ai/job/analog-mixed-signal-ic-design-lead-engineer-phizenix-bengaluru-hpvp5jt5b4qa) — Bengaluru, India - [Future Opportunities at Phizenix – Let's Stay Connected!](https://feeny.ai/job/future-opportunities-at-phizenix-let-s-stay-connected-phizenix-remote-ymyeg9621244)