---
title: 'Senior Digital Design Engineer at Powerlattice Technologies Inc.'
canonical: 'https://feeny.ai/job/senior-digital-design-engineer-powerlattice-technologies-inc-chandler-0kmj9dmzjxj1'
type: 'job'
last_seen: '2026-09-14'
---

# Senior Digital Design Engineer at Powerlattice Technologies Inc.

- **Company:** Powerlattice Technologies Inc.
- **Location:** Chandler, AZ
- **Employment:** full-time
- **Work type:** hybrid
- **Posted:** 2026-08-19
- **Last confirmed live:** 2026-09-14
- **Apply:** https://jobs.ashbyhq.com/powerlattice/1bcf9044-6bf5-4523-9299-243db05118ec

## Job description

Senior or Staff Digital Design Engineer Reports To: Head of Engineering

## About Us

Powerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing.

## About the Role

We are seeking an experienced and hands-on Senior Digital Design Engineer to contribute to the design and implementation of complex digital systems and SoC components. This role offers the opportunity to own significant functional blocks from microarchitecture through RTL development, integration, and implementation while collaborating closely with verification, physical design, and DFT teams. The ideal candidate is passionate about digital design, enjoys solving challenging technical problems, and thrives in a collaborative startup environment where individual contributions have a direct impact on product success.

## Key Responsibilities

Digital Design & RTL Development

- Develop microarchitecture for assigned digital blocks and subsystems
- Design, code, and maintain high-quality, synthesizable RTL
- Evaluate design tradeoffs involving performance, power, area (PPA), and testability
- Participate in design reviews and incorporate feedback into RTL implementation

Integration & Implementation

- Integrate RTL into larger subsystem and SoC environments
- Support lint, CDC/RDC, synthesis, and design quality checks
- Collaborate with physical design teams to resolve implementation issues
- Assist with timing constraint development and timing closure activities
- Support logic equivalence checking (LEC) and implementation debugging
- Participate in functional and timing ECO development when required

Design Quality

- Ensure designs meet functional, timing, power, and DFT requirements
- Support silicon bring-up, validation, and post-silicon debug activities
- Analyze and resolve design issues throughout the development lifecycle

Cross-Functional Collaboration

- Work closely with verification, DFT, physical implementation, firmware, and systems teams
- Partner with architects and senior technical leaders to refine design requirements
- Contribute to continuous improvement of design methodologies and development processes
- Mentor junior engineers and share technical knowledge within the team (Staff level)

## Qualifications

This is a Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouver and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline
- 6+ years of digital IC design experience
- Strong hands-on RTL development experience using Verilog or SystemVerilog
- Experience designing digital blocks for complex SoCs or ASICs
- Solid understanding of:
- RTL design and microarchitecture
- SoC integration and standard on-chip interfaces
- Clocking, resets, CDC/RDC methodologies
- Synthesis and physical implementation considerations
- Timing constraints (SDC) and timing closure
- Experience with industry-standard EDA tools (Synopsys and/or Cadence)
- Strong debugging, analytical, and problem-solving skills
- Excellent communication and collaboration skills

## Preferred

- Experience with DFT methodologies including scan insertion and MBIST
- Experience with logic equivalence checking (LEC)
- Familiarity with static timing analysis (STA)
- Experience with UPF/CPF low-power methodologies
- Exposure to advanced semiconductor process nodes
- Experience supporting silicon bring-up and post-silicon debug
- Formal verification experience is a plus

## Compensation & Benefits

Anticipated annual base salary for Member of Technical Staff: $150,000 - $200,000

- Stock option grant
- Comprehensive benefits package including health, dental, vision, and 401(k)

## About Powerlattice Technologies Inc.

## Company Overview
- **One-liner**: PowerLattice reimagines power delivery for next-generation AI accelerators with the industry’s first power delivery chiplet, integrating voltage regulation directly into the processor package to break the AI power wall.
- **Entity Type**: Private (raised $25M in funding; stage not publicly specified)
- **Headquarters**: United States (specific city not publicly disclosed; offices in two US locations)
- **Founded**: Year not publicly available
- **Founders**: Dr. Peng Zou, Gang Ren, Sujith Dermal

## Core Business
- Primary industry: Semiconductor power delivery for AI accelerators, GPUs, and data-center processors
- Target customers: B2B – data center operators, AI hardware manufacturers, SoC designers
- Mission: “Reimagining power delivery for next-generation AI accelerators” by tightly integrating power and compute to achieve breakthrough performance, efficiency, and scalability.

## Products & Services
- **[Power Delivery Chiplet (Rainier micro-IVR architecture)]**: A monolithic chiplet that combines miniaturized on-die magnetic inductors, advanced control circuits, and a programmable software layer. It delivers voltage regulation directly inside the processor package, enabling 2-3X performance per watt, >50% reduction in power loss, and significantly extended system lifetime. Hardware product (chiplet) with software configurability.

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Total funding of $25M (announced on company website)
- **Notable Investors/Partners**: Investors include Steve Fu; board of directors includes Pat Gelsinger (former Intel CEO). Additional partners/backers not publicly detailed.
- **Growth Signals**: Early-stage company with a small team (10–20 employees per conflicting reports from BuiltIn); first-of-its-kind product targeting the urgent “power wall” problem in AI data centers; founders bring deep experience from Qualcomm, NUVIA, Intel, Huawei, and other top semiconductor firms.

## Competitive Advantages
- **On-die magnetic inductors** – miniaturized proprietary inductors integrated at the chip level, enabling tight coupling between power and compute.
- **Chiplet architecture** – scalable, configurable, and adaptable to any SoC power topology; can be embedded in substrates or interposers.
- **Order-of-magnitude reduction in power noise** and >50% reduction in effective compute power needs.
- **Performance uplift** – under fixed data center power budgets, translates into 2X or more raw performance uplift.
- **Founding team’s deep domain expertise** in power management, IVR, and high-volume IC design for tier-one customers (Apple, Samsung, Amazon).

## Strategic Focus
- Current priority: Productizing the power delivery chiplet and achieving design wins with major AI accelerator and GPU customers.
- Long-term direction: Scaling the chiplet architecture for next-generation data-center processors and expanding into broader high-performance computing markets.
- Focus on breaking the “power wall” that limits AI compute density and data center efficiency.

## Why Work Here
- **Culture**: Small, focused team working on hard problems at the intersection of hardware and innovation. Emphasizes curiosity, hands-on work, and real-world impact.
- **Work environment**: Remote-first with hybrid options; two US offices available. BuiltIn lists roles as “Remote Workspace” and “Hybrid”.
- **Perks**: Equity (stock options) offered. The company values thoughtful engineering and believes better power delivery can unlock new computing possibilities.
- **Engineering culture**: Deep technical challenges in analog/mixed-signal IC design, magnetic materials, system integration, and software. Opportunities to work with industry veterans and shape a groundbreaking product from early stage.

## Sources
1. [powerlatticeinc.com](https://powerlatticeinc.com/)
2. [powerlatticeinc.com/about](https://powerlatticeinc.com/about)
3. [powerlatticeinc.com/careers](https://powerlatticeinc.com/careers)
4. [builtin.com](https://builtin.com/company/powerlattice-inc)
5. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/powerlattice)

## Other roles at Powerlattice Technologies Inc.

- [Applications Engineer](https://feeny.ai/job/applications-engineer-powerlattice-technologies-inc-chandler-j622nx343qje) — Chandler, AZ
- [Technical Program Manager - Silicon Development](https://feeny.ai/job/technical-program-manager-silicon-development-powerlattice-technologies-inc-hq-gc6h651g9nrf) — HQ / Vancouver, Canada
- [Sr. Field Applications Engineer - Power Delivery](https://feeny.ai/job/sr-field-applications-engineer-power-delivery-powerlattice-technologies-inc-jff9zvs9n5kh) — Silicon Valley, CA
- [Senior/Staff Analog IC Design Engineer](https://feeny.ai/job/senior-staff-analog-ic-design-engineer-powerlattice-technologies-inc-hq-am0zm00an62v) — HQ / Vancouver, Canada
- [Senior or Staff Hardware Design Engineer](https://feeny.ai/job/senior-or-staff-hardware-design-engineer-powerlattice-technologies-inc-chandler-ctnc8vpgay2h) — Chandler, AZ
- [Senior Digital Design Engineer](https://feeny.ai/job/senior-digital-design-engineer-astera-labs-toronto-msea5r66yqk1) — Toronto, Canada
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