---
title: 'Senior Engineering Program Manager at Velaura'
canonical: 'https://feeny.ai/job/senior-engineering-program-manager-velaura-santa-clara-73yycn9ge0f3'
type: 'job'
last_seen: '2026-09-11'
---

# Senior Engineering Program Manager at Velaura

- **Company:** Velaura
- **Location:** Santa Clara, CA
- **Compensation:** $200k–$300k
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-08-09
- **Last confirmed live:** 2026-09-11
- **Apply:** https://jobs.lever.co/velaura/563ef2e6-d80d-4401-8ea9-d41ca6e1d543

## Job description

## Role Overview

Velaura is designing the compute silicon that will power the next generation of robots, autonomous systems, and intelligent machines operating in the physical world. As Senior Engineering Program Manager, you will drive execution of our Physical AI System-on-Chip (SoC) program across its full scope: silicon development, platform hardware, software, and third-party IP (3PIP) vendors. This role is the connective tissue of the program. You will own the integrated program schedule from architecture through tapeout, silicon bring-up, and platform/software readiness— coordinating internal engineering teams, external IP providers, and manufacturing partners. You will surface risks early, drive decisions to closure, and keep a complex, multi-disciplinary program moving at startup speed.

## Responsibilities

- Own the end-to-end SoC program plan: define and maintain the integrated schedule spanning architecture, RTL design, verification, physical design, tapeout, silicon bring-up, and production readiness.
- Drive platform and software program execution in parallel with silicon—board development, firmware, drivers, SDK, and system validation—so that software and platform readiness track silicon milestones.
- Manage third-party IP (3PIP) vendor engagements: track licensing and contract milestones, deliverable schedules, quality metrics, errata, and integration dependencies across multiple IP providers.
- Run program-level rhythm: milestone reviews, cross-functional syncs, executive status reporting, and decision logs that keep stakeholders aligned and accountable.
- Identify, quantify, and drive mitigation of program risks across silicon, platform, software, and vendor workstreams; escalate with data and proposed options, not just problems.
- Coordinate external execution partners—foundry, OSAT, design services, and platform manufacturing—on schedules, deliverables, and dependencies.
- Build the program management processes, tools, and templates for a growing engineering organization, and mentor teams on execution discipline

Required Qualifications

- 10+ years of engineering program management experience in semiconductors, with at least one complex SoC program managed from architecture through tapeout and bring-up.
- Demonstrated experience managing programs that span silicon, platform hardware, and software—understanding the distinct execution rhythms and dependencies of each.
- Hands-on experience managing third-party IP vendors, including deliverable tracking, milestone-based contracts, and cross-vendor dependency management.
- Working technical fluency in SoC development: ability to engage credibly in discussions of RTL milestones, verification coverage, physical design closure, DFT, and software/firmware bring-up.
- Expert command of program management fundamentals: schedule development and critical-path analysis, risk management, change control, and stakeholder communication.
- Proven ability to influence without authority across engineering, vendor, and executive audiences; excellent written and verbal communication skills.
- Bachelor's degree in Electrical/Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.

## Preferred Qualifications

- Experience with programs in advanced process nodes and with foundry/OSAT engagement models.
- Experience in edge AI, automotive, robotics, or other embedded/safety-adjacent domains, including familiarity with quality and functional-safety development processes.
- Experience at an early-stage or high-growth company, building program management practices from the ground up.
- Master's degree in engineering or business.

Why Velaura? Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world. This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

## Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans. Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: careers@velaura.ai. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

## About Velaura

## Company Overview
- **One-liner**: Velaura (formerly Auradine) is a semiconductor and systems company building ultra-low-power compute infrastructure for AI workloads across cloud, edge, and physical AI applications.
- **Entity Type**: Private (Series C, $314M total funding)
- **Headquarters**: Santa Clara, California, USA
- **Founded**: 2023 (as Auradine; rebranded to Velaura AI in 2026)
- **Founders**: Co-founded by Rajiv Khemani (CEO), YJ Kim (President, Products), Sanjay Gupta (President, Strategy & GTM), and Manu Gulati (Chief Development Officer)

## Core Business
- **Primary Industry**: Semiconductor design, AI compute infrastructure, ultra-low-power ASICs
- **Target Customers**: Hyperscale data centers, AI/ML platform providers, edge computing companies, and physical AI (robotics, automotive) OEMs — primarily **B2B Enterprise**
- **Mission**: To deliver proven, breakthrough, ultra-low-power compute for cloud, edge, and physical AI applications, solving the power bottleneck that constrains AI scaling.

## Products & Services
- **Proprietary Ultra-Low-Power Digital Design Technology**: Patented IP and toolflow that reduces power consumption of arithmetic operations by 2–4x on leading process nodes, translating to ~$650–$1,300/chip in power savings over 3 years. Output is optimized GDS or chiplets.
- **Custom AI Accelerators (ASICs)**: Full-custom silicon solutions for AI inference and training workloads, co-designed with customers (RTL input → optimized GDS).
- **Engagement Model**: Customer provides RTL design and priorities; Velaura applies its proprietary methodology, low-voltage libraries, and custom circuit expertise to deliver power-optimized chip designs with proven yield and reliability.

## Market Standing
- **Valuation/Market Cap**: Not publicly disclosed (private company)
- **Key Metric**: **$314M total funding** across 4 rounds
  - Series A (2023): $71M from 6 investors
  - Debt Financing (2023): $10M
  - Series B (2024): $80M from 7 investors
  - Series C (2025): $153M from 8 investors
- **Notable Investors/Partners**: Backed by top-tier VCs (specific names not publicly listed; investors include firms with deep semiconductor expertise) — talent sources include Qualcomm, Arm, Apple, Google, NVIDIA, Intel, Palo Alto Networks, Stripe
- **Growth Signals**:
  - Rebranded from Auradine to Velaura AI in August 2026, signaling strategic expansion into AI compute
  - Added Manu Gulati (ex-NUVIA co-founder, Apple/Google silicon architect) as Co-founder & Chief Development Officer
  - Added Aditya Grover (Co-founder & CTO of Inception, Stanford PhD, part of the team that invented Diffusion models) as Founding Advisor
  - Workforce of 42 employees growing at +4.3% monthly; headcount split ~47% US / 39% India
  - Offices in Santa Clara, CA (HQ) and additional US location, with hiring across hardware and software engineering in Bangalore, Austin, and Boston

## Competitive Advantages
- **Patented ultra-low-power digital design technology** field-proven over multiple years across tens of millions of ASICs deployed with world-class yield and reliability
- **Founding team with exceptional pedigree**: seasoned entrepreneurs and technologists from Qualcomm, Marvell, NVIDIA, Intel, Palo Alto Networks, Apple, Google, and NUVIA (acquired by Qualcomm for ~$1.5B)
- **Systems-level thinking**: combines deep silicon expertise with AI/ML domain knowledge to tackle power as the primary bottleneck for AI at scale
- **Engagement model** that allows customers to leverage Velaura’s IP without fully outsourcing chip design — outputs optimized GDS or chiplets on latest process nodes

## Strategic Focus
- **Scale ultra-low-power compute across three domains**: cloud data centers, edge/enterprise, and physical AI (robotics, autonomous systems)
- **Hire aggressively** for engineering leadership: compiler development, platform software, CAD/methodology, RTL, design verification, advanced packaging, AI architecture, and hardware/software co-design
- **Productize its proprietary IP** into standard offerings for hyperscalers and AI chip companies
- **Continue raising capital** (largest round was $153M Series C in April 2025) to fund expansion

## Why Work Here
- **Culture**: Deep engineering DNA and systems-level thinking — the team is solving one of AI’s hardest physical constraints (power) with proven silicon technology
- **Growth trajectory**: Rapidly scaling startup (42 employees, +4.3% monthly headcount growth, $314M raised) with a clear path to becoming a key infrastructure provider for the AI era
- **Leadership**: Led by industry veterans (NUVIA, Apple, Google, Qualcomm) who have built billion-dollar silicon companies and products powering billions of devices
- **Work environment**: On-site roles in Santa Clara, CA; Austin, Texas; and Bangalore, India. Remote/hybrid policy not specified but multiple office locations suggest flexible collaboration.
- **Impact**: Opportunity to work on cutting-edge AI hardware design, from architecture through tape-out and deployment, with direct impact on the power efficiency of the world’s largest AI clusters
- **Notable perks**: Not publicly detailed, but the company’s focus on high-end engineering talent suggests competitive compensation, equity, and exposure to top-tier semiconductor and AI technology

## Sources
1. [velaura.ai](https://velaura.ai/introducing-velaura-ai/)
2. [velaura.ai](https://velaura.ai/team/)
3. [velaura.ai](https://velaura.ai/low-power-ai-compute/)
4. [jobs.lever.co/velaura](https://jobs.lever.co/velaura/)
5. [linkedin.com](https://linkedin.com/company/velaura-ai-inc)
6. [wellfound.com](https://wellfound.com/company/velaura-ai) (Apollo data extracted on financials and headcount)

SUGGESTED_INDUSTRY: semiconductor-manufacturing-robotics-ai-infrastructure
_(Note: The above slug is not in the provided list. Closest match from the list is `artificial-intelligence`. However, given the company's core business is semiconductor design and power-efficient AI compute infrastructure, `manufacturing-robotics` or `infrastructure` also fit. For strict adherence to the provided list: `artificial-intelligence` is the best single choice.)_

## Other roles at Velaura

- [Office Admin / Receptionist](https://feeny.ai/job/office-admin-receptionist-velaura-santa-clara-asc5tq6ff9ze) — Santa Clara, CA
- [Sr Engineer CAD Pre-Silicon Front End](https://feeny.ai/job/sr-engineer-cad-pre-silicon-front-end-velaura-santa-clara-91g66vhzqqt3) — Santa Clara, CA
- [Director of IT Infrastructure & Operations](https://feeny.ai/job/director-of-it-infrastructure-operations-velaura-santa-clara-46t1yb690v9g) — Santa Clara, CA
- [RTL Power Engineer](https://feeny.ai/job/rtl-power-engineer-velaura-santa-clara-jyj4n03rckrf) — Santa Clara, CA
- [Design Verification Engineer- AI Accelerator](https://feeny.ai/job/design-verification-engineer-ai-accelerator-velaura-santa-clara-15tk23smaz5x) — Santa Clara, CA
- [Design Verification Engineer- CPU](https://feeny.ai/job/design-verification-engineer-cpu-velaura-santa-clara-d1bkx2h2dj9g) — Santa Clara, CA
- [Physical Verification Engineer (Staff / Sr. Staff)](https://feeny.ai/job/physical-verification-engineer-staff-sr-staff-velaura-bengaluru-4k6ypqtyjv23) — Bengaluru, India
- [CAD & Engineering Infrastructure Lead](https://feeny.ai/job/cad-engineering-infrastructure-lead-velaura-santa-clara-eca75sba2s9n) — Santa Clara, CA
- [Senior Technical Recruiter – Engineering](https://feeny.ai/job/senior-technical-recruiter-engineering-velaura-santa-clara-v66mv6d4ghqd) — Santa Clara, CA
- [Principal AI SoC Runtime Software Architect](https://feeny.ai/job/principal-ai-soc-runtime-software-architect-velaura-santa-clara-bf6ceyep3azn) — Santa Clara, CA