--- title: 'Senior Foundry Integration Engineer at nEye.ai' canonical: 'https://feeny.ai/job/senior-foundry-integration-engineer-neye-ai-santa-clara-6s3mws7xah38' type: 'job' last_seen: '2026-09-08' --- # Senior Foundry Integration Engineer at nEye.ai - **Company:** nEye.ai - **Location:** Santa Clara, CA - **Compensation:** $170k–$220k - **Employment:** full-time - **Work type:** onsite - **Posted:** 2026-07-23 - **Last confirmed live:** 2026-09-08 - **Apply:** https://jobs.lever.co/neye-systems-inc./b8215d43-88a8-4856-91a8-50f703923a55 ## Job description ## About us nEye.ai, a well-funded optical switch startup, is poised to revolutionize the future of data centers. nEye’s MEMS-based silicon photonics optical circuit switches (OCS) eliminate critical bottlenecks in AI processing by enabling direct optical connections among thousands of GPUs and memory units. The company's OCS is an ultra-low power consumption, high radix, compact chip-scale design, offering hyperscale data centers enhanced performance, efficiency, and scalability. ## Role Overview We're looking for a detail-oriented Senior Foundry Integration Engineer to own the technical execution of development programs with our external semiconductor foundry partners. This role sits at the intersection of design, layout, process integration, and manufacturing. You'll coordinate engineering wafer runs from layout release through wafer delivery, ensuring tape-ins are complete, process flows are optimized, engineering experiments are well defined, and development data is captured and communicated effectively. This is an excellent opportunity for an engineer with exceptional attention to detail and the ability to coordinate multiple concurrent foundry development programs, engineering lots, and technical deliverables. ## Key Responsibilities Tape-In & Foundry Execution - Own engineering tape-ins from finalized layout through successful release to external foundry partners. - Coordinate cross-functional tape-in readiness across Design, Layout, MEMS Integration, and Process Engineering teams. - Participate in tape-in quality reviews, ensuring layouts, documentation, and process assumptions are complete before release. - Track engineering lots from tape-in through wafer delivery and communicate status across the organization. Development Programs & NPI Management - Define, coordinate, and track engineering split lots to maximize technical learning while optimizing wafer utilization. - Develop and manage short-loop experiments and Design of Experiments (DOEs) to investigate process issues and accelerate development. - Own NPI split management, including technical definition, schedule tracking, wafer tracking, engineering data collection, and results summarization. - Coordinate development activities with foundry engineers to ensure engineering objectives and timelines are achieved. Process Flow Review - Review process flows alongside layout prior to tape-in to identify potential manufacturability or integration risks. - Evaluate process assumptions, mask layers, and layout interactions before fabrication. - Work closely with MEMS Integration Engineers to ensure process flows support device requirements. - Help identify opportunities to improve process robustness before engineering wafers are fabricated. Process Flow Evaluation & Simulation - Perform process flow evaluations using layout review tools such as KLayout. - Analyze layout layers and process interactions to identify potential fabrication issues before tape-in. - Support simulation of process flow alternatives to improve manufacturability and development efficiency. - Grow into ownership of process flow modeling and simulation capabilities as the foundry development program expands. Required Experience and Skills - BS, MS, or PhD in Electrical Engineering, Materials Science, Physics, Mechanical Engineering, Chemical Engineering, or related discipline. - 7+ years of experience working with semiconductor process development or process integration. - 7+ years of experience collaborating with semiconductor foundries or external manufacturing partners. - MEMS or silicon photonics manufacturing experience. - Understanding of semiconductor fabrication process flows. - Experience defining or supporting Design of Experiments (DOE) activities. - Strong organizational skills with the ability to manage multiple parallel engineering activities. - Excellent written and verbal communication skills. ## Preferred Experience and Skills - Experience supporting tape-ins or engineering wafer programs. - Familiarity with semiconductor layouts and mask data. - Experience reviewing process flows for manufacturability. - Knowledge of KLayout or similar layout visualization tools. - Experience with process simulation or process flow modeling. - Familiarity with commercial semiconductor foundries. - Professional proficiency in Mandarin Chinese is a plus to support technical collaboration with overseas foundry partners. nEye is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law. ## About nEye.ai ## Company Overview - **One-liner**: nEye.ai develops ultra-low-power MEMS-based silicon photonic optical circuit switches (OCS) that eliminate connectivity bottlenecks in AI data centers, enabling direct optical links among thousands of GPUs. - **Entity Type**: Private (Series C funding stage) - **Headquarters**: Santa Clara, California, United States - **Founded**: 2020 - **Founders**: Ashish Vengsarkar (CEO), Ming Wu (Chief Scientist & Co-Founder), Tae Joon Seok (CTO & Co-Founder) ## Core Business - **Primary industry**: Semiconductor manufacturing (silicon photonics) / AI data center infrastructure - **Target customers**: Hyperscale data centers, cloud providers, AI/ML infrastructure operators (B2B, Enterprise) - **Mission**: To transform data center networks through innovative optical circuit switching technology, solving the most challenging problems in AI infrastructure. ## Products & Services - **[SuperSwitch](https://www.neye.ai)**: A chip-scale, high-radix optical circuit switch leveraging MEMS-based silicon photonics. It enables direct optical connections among GPUs and memory units, dramatically reducing power consumption and latency compared to electrical switches. Type: Hardware (silicon photonic switch). ## Market Standing - **Valuation/Market Cap**: Not publicly disclosed - **Key Metric**: Total funding of **$152.5M** across four rounds (Series A, B, C, and a corporate round) as of April 2026 - **Notable Investors/Partners**: Sutter Hill Ventures (led Series C, $80M, April 2026), CapitalG (led Series B, $58M, May 2025), TEDA (led Series A, $14.5M, September 2023) - **Growth Signals**: Headcount grew **+164.7% YoY** to 36 employees; 12 active job postings (up 300% YoY); filed 12 patents in photonics, fiber optics, and optical devices; key hires from Google, AWS, Ayar Labs, and Intel. ## Competitive Advantages - **MEMS + Silicon Photonics Integration**: Combines micro-electromechanical systems (MEMS) with silicon photonics on a single chip, enabling ultra-low power, high-radix switching in a compact form factor. - **Founding Team Depth**: Led by industry veterans with decades of experience at Bell Labs, UC Berkeley, Google, and successful optical startups (Photuris, Nistica). Chief Scientist Ming C. Wu is a renowned professor at UC Berkeley. - **Patented Technology**: 12 granted/pending patents covering lidar, photonic switch arrays, and optical devices. - **Hyperscaler Relevance**: Directly addresses the critical bottleneck in AI cluster networking, a problem actively being tackled by major cloud providers. ## Strategic Focus - **Scaling Engineering & Operations**: Heavily hiring across MEMS design, photonics, silicon photonics layout, test systems, and lab operations to accelerate product development and deployment. - **Hyperscale Deployment**: Targeting volume production and integration into the world’s largest AI data centers, leveraging team members’ prior experience at Google and AWS. - **Product Maturation**: Moving from prototype to commercial-grade SuperSwitch, with emphasis on reliability, yield, and cost efficiency. ## Why Work Here - **Mission-Driven**: Tackle one of the hardest problems in AI infrastructure – optical connectivity at scale. - **On-Site Culture**: Roles are based in Santa Clara, CA (with an additional Berkeley office), fostering close collaboration among a tight-knit, highly technical team. - **Impact & Ownership**: Small team (~36 people) means engineers have broad responsibility and direct influence on product direction. - **Veteran Leadership**: Work alongside former Google, Bell Labs, and successful startup leaders who have raised over $100M and achieved multiple exits. - **Growth Trajectory**: Rapid headcount growth and significant venture backing signal a company in an aggressive scaling phase, offering career advancement opportunities. ## Sources 1. [LinkedIn – nEye Systems Company Page](https://linkedin.com/company/neye-systems) 2. [CB Insights – nEye Systems Profile](https://www.cbinsights.com/company/neye-systems) 3. [nEye.ai About Us](https://www.neye.ai/about-us) 4. [nEye.ai Join Us / Careers](https://www.neye.ai/join-us) 5. [Lever Jobs – nEye Systems Openings](https://jobs.lever.co/neye-systems-inc) ## Other roles at nEye.ai - [Senior Silicon Photonics Designer](https://feeny.ai/job/senior-silicon-photonics-designer-neye-ai-santa-clara-eqqy2cje2bz7) — Santa Clara, CA - [Photonics Test Technician](https://feeny.ai/job/photonics-test-technician-neye-ai-santa-clara-5w5004d6mgd3) — Santa Clara, CA - [Senior Mechanical Engineer](https://feeny.ai/job/senior-mechanical-engineer-neye-ai-santa-clara-xk1zjs81pyr2) — Santa Clara, CA - [Principal Systems Packaging & Assembly Engineer](https://feeny.ai/job/principal-systems-packaging-assembly-engineer-neye-ai-santa-clara-mbmxte9kq10c) — Santa Clara, CA - [Principal Packaging Engineer, Optical Interfaces](https://feeny.ai/job/principal-packaging-engineer-optical-interfaces-neye-ai-santa-clara-r6c27ht76z0w) — Santa Clara, CA - [Principal Wafer Bonding Integration Engineer](https://feeny.ai/job/principal-wafer-bonding-integration-engineer-neye-ai-santa-clara-7q9fv5rjjgcs) — Santa Clara, CA - [Purchasing Specialist](https://feeny.ai/job/purchasing-specialist-neye-ai-santa-clara-d7cs13xv9w7a) — Santa Clara, CA - [Lab Operations, Facilities and Equipment Manager](https://feeny.ai/job/lab-operations-facilities-and-equipment-manager-neye-ai-santa-clara-and-1qv3ypwcxjcm) — Santa Clara and Emeryville, CA - [Director of Finance](https://feeny.ai/job/director-of-finance-neye-ai-santa-clara-xpx7epw3tzrn) — Santa Clara, CA - [Photonics Lab Operator](https://feeny.ai/job/photonics-lab-operator-neye-ai-santa-clara-naj10gc81s1g) — Santa Clara, CA