---
title: 'Senior HPC Developer - RDMA Networking at Clockwork.io'
canonical: 'https://feeny.ai/job/senior-hpc-developer-rdma-networking-clockwork-io-palo-alto-eqz2f7jqd9n0'
type: 'job'
last_seen: '2026-10-19'
---

# Senior HPC Developer - RDMA Networking at Clockwork.io

- **Company:** Clockwork.io
- **Location:** Palo Alto, CA
- **Work type:** onsite
- **Posted:** 2026-10-06
- **Last confirmed live:** 2026-10-19
- **Apply:** https://job-boards.greenhouse.io/clockworksystems/jobs/6218348004

## Job description

## About Clockwork Systems

Clockwork.io – Software Driven Fabrics to increase GPU cluster utilization

Clockwork Systems was founded by Stanford researchers and veteran systems engineers who share a vision for redefining the foundations of distributed computing. As AI workloads grow increasingly complex, traditional infrastructure struggles to meet the demands of performance, reliability, and precise coordination. Clockwork is pioneering a software-driven approach to AI fabrics by delivering cross-stack observability to catch and quickly resolve problems, workload fault tolerance to keep jobs running through failures, and performance acceleration that dynamically routes and paces traffic to avoid congestion.

To learn more, visit[www.clockwork.io](https://www.clockwork.io).

## About the Role

We’re looking for a Senior Systems Engineer – RDMA Networking & Storage to help build and optimize high-performance infrastructure for AI and HPC systems. You’ll work across RDMA networking and storage data paths, spanning compute hosts, NICs, DPUs, smart switches, storage systems, and the Linux software stack. The work includes RoCE networking, NVMe-over-Fabrics, congestion control, performance optimization, programmable network hardware, and debugging complex interactions across hardware and software. This role is ideal for an experienced systems engineer who enjoys working close to the hardware, diagnosing difficult performance problems, and building reliable systems where latency, throughput, and network behavior matter.

## What You’ll Do

- Design, build, and optimize high-performance RDMA networking and storage systems
- Work with RoCE, RDMA Verbs, and NVMe-over-Fabrics
- Develop systems that leverage DPUs, SmartNICs, and programmable switches for packet processing, telemetry, control, and data-path acceleration
- Develop and optimize software using queue pairs, completion queues, memory registration, zero-copy I/O, and other RDMA primitives
- Debug performance and reliability issues across applications, Linux kernel, drivers, NICs, DPUs, switches, and storage systems
- Analyze network and storage behavior including latency, throughput, queueing, congestion, packet loss, retransmissions, and flow control
- Develop mechanisms to improve network performance and congestion behavior in high-bandwidth RDMA fabrics
- Build tooling and instrumentation to understand end-to-end performance across compute, network, and storage
- Profile and tune systems across PCIe, NUMA, CPU, memory, NIC, DPU, network, and storage boundaries
- Own major components from design through implementation, performance validation, and deployment

## What You Bring

- 5+ years of experience in systems, networking, storage, HPC, or other performance-critical software development
- Strong proficiency in low-level C/C++
- Strong understanding of RDMA networking, including RoCE and RDMA Verbs
- Strong understanding of networking fundamentals, including packet processing, queues, congestion, and flow control
- Experience debugging low-level Linux networking, storage, or driver behavior
- Familiarity with concepts such as DMA, memory registration, queue pairs, completion queues, interrupts/polling, and zero-copy I/O
- Experience profiling and optimizing latency- and throughput-sensitive systems
- Ability to reason across hardware and software boundaries and independently debug complex system-level problems
- Strong ownership and comfort working in a small, fast-moving engineering team

Bonus Points

- Experience with DPUs, SmartNICs, or programmable network hardware
- Experience with platforms such as NVIDIA BlueField or programmable switch environments
- Experience with P4, switch SDKs, or in-network packet processing
- Experience with NVMe, NVMe-oF, NVMe/RDMA, or NVMe/TCP
- Experience with SPDK, DPDK, or other userspace I/O frameworks
- Experience with Linux NVMe and RDMA subsystems
- Experience with congestion control, including DCQCN, ECN, PFC, or related mechanisms
- Experience tuning NVIDIA/Mellanox ConnectX NICs and RoCE fabrics
- Experience working with high-performance switches and data-center network fabrics
- Experience with PCIe, NUMA, huge pages, DMA, or CPU affinity optimization
- Experience with performance profiling, tracing, or observability tooling
- Background in AI infrastructure, HPC clusters, distributed storage, or large-scale data-center systems

Enjoy

- Challenging, technically deep projects
- A friendly and inclusive workplace culture
- Competitive compensation
- A great benefits package
- Catered lunch

Compensation for this position will vary based on the skills and experience you bring, as well as internal equity considerations. For candidates hired at the posted level, the expected base salary range is $150,000–$230,000. The offered compensation package may also include stock options or other equity awards, subject to Clockwork’s equity program and applicable approvals. Clockwork Systems is an equal opportunity employer. We are committed to building world-class teams by welcoming bright, passionate individuals from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, ancestry, religion, age, sex, sexual orientation, gender identity or expression, national origin, disability, or protected veteran status. We believe diversity drives innovation, and we grow stronger together.

## About Clockwork.io

## Company Overview

- **One-liner**: Clockwork builds software-driven AI fabrics that optimize GPU clusters for fault tolerance, deterministic performance, and higher utilization, working across any network (InfiniBand, RoCE, Ethernet) and any GPU vendor.
- **Entity Type**: Private (Series B)
- **Headquarters**: Palo Alto, California, United States
- **Founded**: 2018 (originally founded as Tick Tock Networks, renamed Clockwork Systems in 2021)
- **Founders**: Balaji Prabhakar, Yilong Geng, Deepak Merugu, Suresh Vasudevan (CEO), Mendel Rosenblum (Chief Scientist)

## Core Business

- **Primary industry**: AI infrastructure / data center networking / GPU cluster optimization
- **Target customers**: B2B, targeting hyperscalers, cloud providers, enterprises, and AI labs running large-scale distributed training and inference workloads
- **Mission/purpose**: To eliminate communication bottlenecks in AI fabrics, making AI workloads resilient, performant, and efficient — all through software alone.

## Products & Services

- **Clockwork FleetIQ**: A software-driven AI fabric that improves GPU cluster utilization and job completion times by 1.1–1.5x, reduces disruptive failures by over 90%, and provides observability, fault tolerance, and dynamic traffic control. Works across any network and GPU vendor.
- **Clockwork TorchPass**: A fault-tolerance framework for AI training that, according to a SemiAnalysis report, is the only approach that does not degrade training performance, recovering millions in wasted compute annually.
- **Live GPU Migration**: Introduced in June 2026, enables AI workloads to continue running through failures by migrating GPU state live, minimizing downtime.
- **Global Clock Sync**: Software-based near-nanosecond clock synchronization across distributed components, enabling precise telemetry and one-way delay measurement.
- **Distributed State Transfer**: Captures and transfers distributed network/communication state (model parameters, NCCL communicators, etc.) to support path failover and live GPU migration.
- **Dynamic Traffic Control**: Programmable traffic steering and pacing at the packet level to relieve congestion and bound tail latencies.

## Market Standing

- **Total Funding**: $41.5M raised (Series B, with $20.5M raised approximately 10 months prior to June 2026)
- **Valuation**: Not publicly disclosed
- **Notable Investors**: Lead Series A investor New Enterprise Associates (NEA). Individual investors include Lip Bu Tan (CEO of Intel), Diane Greene (former CEO of VMware), John Chambers (former CEO/Executive Chairman of Cisco), John Hennessy (former President of Stanford, Chairman of Alphabet), Ram Shriram (Trustee of Stanford and Alphabet), Jerry Yang (AME Cloud Ventures, co-founder of Yahoo!).
- **Growth Signals**: Launched "You Only Compute Once" (YOCO) contractual commitment to end GPU waste; TorchPass validated by SemiAnalysis; released Live GPU Migration capability; active hiring with 9 open roles across engineering, sales, and solutions engineering; CEO interview in June 2026.

## Competitive Advantages

- **Vendor-neutral software-only approach**: Operates across any network fabric (InfiniBand, RoCE, Ethernet) and any GPU vendor — no proprietary hardware required.
- **Foundational research from Stanford**: The Huygens clock synchronization system, developed by co-founder Yilong Geng during his PhD, provides near-nanosecond precision that underpins the entire platform.
- **Unique fault-tolerance without performance loss**: TorchPass is claimed to be the only fault-tolerance framework that does not cost training performance, according to third-party analysis.
- **Live GPU migration**: Allows workloads to survive failures by moving GPU state in real time, a capability not commonly available in competing solutions.
- **Strong advisory network**: Backed by luminaries like Diane Greene, John Chambers, and John Hennessy, providing deep industry credibility.

## Strategic Focus

- **Scale product adoption**: Expanding from early hyperscaler and enterprise deployments to broader market, with a focus on large-scale AI clusters.
- **Deepen observability and automation**: Continuing to enhance the observe-decide-act control loop for autonomic collective communications.
- **Expand global sales and partnerships**: Hiring senior account executives in Europe and solutions engineers in New York, indicating geographic expansion.
- **Build finance and marketing infrastructure**: Recent hires include VP of Finance Alison Qu and VP of Growth Marketing Anita Pandey, signaling preparation for further growth.

## Why Work Here

- **High-impact problem**: Solving fundamental communication bottlenecks in AI infrastructure, directly affecting GPU utilization and job completion times for the largest AI workloads.
- **Strong leadership**: CEO Suresh Vasudevan previously led Nimble Storage from startup to IPO and acquisition by HPE, and was CEO of Sysdig. Co-founders include Stanford professors and VMware co-founder Mendel Rosenblum.
- **Culture**: Emphasizes that "Behind every packet, there’s a person." Perks include free lunch, free gym, TGIFs, and comprehensive benefits.
- **Work policy**: Mix of onsite (Palo Alto, San Francisco) and remote (e.g., New York) roles, with most engineering roles onsite.
- **Recent funding and growth**: Series B stage with $41.5M raised and active hiring indicates strong runway and momentum.

## Sources

1. [clockwork.io/about-us](https://clockwork.io/about-us/)
2. [clockwork.io](https://clockwork.io/)
3. [clockwork.io/careers](https://clockwork.io/careers/)
4. [greenhouse.io - job board](https://job-boards.greenhouse.io/clockworksystems/jobs/5870086004)
5. [cbinsights.com - Clockwork profile](https://www.cbinsights.com/company/clockwork-3)

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