---
title: 'Senior or Staff Design Verification Engineer at Powerlattice Technologies Inc.'
canonical: 'https://feeny.ai/job/senior-or-staff-design-verification-engineer-powerlattice-technologies-inc-hq-vx9qh10txfcw'
type: 'job'
last_seen: '2026-11-02'
---

# Senior or Staff Design Verification Engineer at Powerlattice Technologies Inc.

- **Company:** Powerlattice Technologies Inc.
- **Location:** HQ / Vancouver, Canada
- **Employment:** full-time
- **Work type:** hybrid
- **Posted:** 2026-09-23
- **Last confirmed live:** 2026-11-02
- **Apply:** https://jobs.ashbyhq.com/powerlattice/c4c0cf5f-3bfb-4b2d-9606-a273bf0a6353

## Job description

Design Verification Lead Reports To: Head of Engineering

## About Us

Powerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing.

## About the Role

We are seeking an experienced and hands-on Design Verification Lead to spearhead verification activities for complex SoC/IP designs, developing scalable SystemVerilog-based verification environments, verification strategies, reusable test infrastructure, and automated regression flows. This position drives functional verification from RTL through gate-level simulation, including coverage closure, assertions, timing verification, and debug. They will collaborate closely with RTL, analog, architecture, and silicon validation teams to identify and resolve design issues.

## Key Responsibilities

- Lead verification planning and execution for complex digital and mixed-signal subsystems, including defining verification strategies, test scenarios, coverage goals, and signoff criteria.
- Architect, develop, and maintain SystemVerilog-based verification environments and reusable verification infrastructure.
- Develop directed, constrained-random, regression, and corner-case tests to verify functional requirements and design specifications.
- Develop reusable verification components and protocol-based test infrastructure for I2C/I3C, SPI, JTAG, AMBA, and OBI interfaces.
- Perform and support Clock Domain Crossing (CDC) verification for async and sync clock-domain interfaces.
- Develop and maintain UVM-based infrastructure and RAL models where applicable.
- Develop checkers, scoreboards, reference models, assertions, and functional coverage to provide comprehensive verification of design behavior.
- Perform RTL and gate-level simulation, including SDF-annotated GLS, to identify functional, timing, initialization, reset, and connectivity issues.
- Develop and optimize regression and GLS flows using Xcelium and VCS.
- Analyze functional and code coverage and drive coverage closure by identifying verification gaps and developing targeted tests.
- Debug complex RTL, testbench, simulation, and gate-level failures using waveform and log analysis.
- Work closely with RTL designers, analog designers, architects, and silicon validation teams to reproduce issues, determine root cause, and drive resolution.
- Review specifications and RTL to identify corner cases, interface issues, reset/clocking problems, and potential functional gaps.
- Translate silicon validation findings into simulation-based verification scenarios and regression tests.
- Provide technical leadership to a team of verification engineers. Mentor the team in verification methodologies, tools, and coverage improvements.

## Qualifications

This is a Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouver and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.

- Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
- 10+ years of experience in digital verification of SoCs with proven ownership of subsystems or full-chip verification.
- Solid Understanding of:
- Digital design fundamentals, FSMs, CDC, RDC, mixed-signal subsystems, and SoC integration.
- Industry-standard protocols including AMBA, I²C, I3C, SPI, JTAG, and OBI.
- Strong Expertise in:
- Verilog, SystemVerilog, UVM and class-based verification methodologies.
- Constrained-random, coverage-driven verification, regression automation, and verification signoff.
- SystemVerilog Assertions (SVA), formal verification techniques.
- Python, Perl, and UNIX/Linux shell scripting for automation.
- Hands-on experience developing testbenches, drivers, monitors, scoreboards, assertions, and reusable verification IP.
- Strong analytical and problem-solving skills, with the ability to debug complex issues, communicate clearly, mentor engineers, lead technical initiatives, and cross-functional collaboration skills.
- Experience with industry-standard EDA tools (Synopsys, Cadence)

## Preferred Qualifications

- Working knowledge of PMIC architectures and power management principles.
- Experience with formal verification techniques

## Compensation & Benefits

Anticipated annual base salary for Member of Technical Staff: $160k - $190k

- Stock option grant
- Comprehensive benefits package including health, dental, vision, and 401(k)

## About Powerlattice Technologies Inc.

## Company Overview
- **One-liner**: PowerLattice reimagines power delivery for next-generation AI accelerators with the industry’s first power delivery chiplet, integrating voltage regulation directly into the processor package to break the AI power wall.
- **Entity Type**: Private (raised $25M in funding; stage not publicly specified)
- **Headquarters**: United States (specific city not publicly disclosed; offices in two US locations)
- **Founded**: Year not publicly available
- **Founders**: Dr. Peng Zou, Gang Ren, Sujith Dermal

## Core Business
- Primary industry: Semiconductor power delivery for AI accelerators, GPUs, and data-center processors
- Target customers: B2B – data center operators, AI hardware manufacturers, SoC designers
- Mission: “Reimagining power delivery for next-generation AI accelerators” by tightly integrating power and compute to achieve breakthrough performance, efficiency, and scalability.

## Products & Services
- **[Power Delivery Chiplet (Rainier micro-IVR architecture)]**: A monolithic chiplet that combines miniaturized on-die magnetic inductors, advanced control circuits, and a programmable software layer. It delivers voltage regulation directly inside the processor package, enabling 2-3X performance per watt, >50% reduction in power loss, and significantly extended system lifetime. Hardware product (chiplet) with software configurability.

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Total funding of $25M (announced on company website)
- **Notable Investors/Partners**: Investors include Steve Fu; board of directors includes Pat Gelsinger (former Intel CEO). Additional partners/backers not publicly detailed.
- **Growth Signals**: Early-stage company with a small team (10–20 employees per conflicting reports from BuiltIn); first-of-its-kind product targeting the urgent “power wall” problem in AI data centers; founders bring deep experience from Qualcomm, NUVIA, Intel, Huawei, and other top semiconductor firms.

## Competitive Advantages
- **On-die magnetic inductors** – miniaturized proprietary inductors integrated at the chip level, enabling tight coupling between power and compute.
- **Chiplet architecture** – scalable, configurable, and adaptable to any SoC power topology; can be embedded in substrates or interposers.
- **Order-of-magnitude reduction in power noise** and >50% reduction in effective compute power needs.
- **Performance uplift** – under fixed data center power budgets, translates into 2X or more raw performance uplift.
- **Founding team’s deep domain expertise** in power management, IVR, and high-volume IC design for tier-one customers (Apple, Samsung, Amazon).

## Strategic Focus
- Current priority: Productizing the power delivery chiplet and achieving design wins with major AI accelerator and GPU customers.
- Long-term direction: Scaling the chiplet architecture for next-generation data-center processors and expanding into broader high-performance computing markets.
- Focus on breaking the “power wall” that limits AI compute density and data center efficiency.

## Why Work Here
- **Culture**: Small, focused team working on hard problems at the intersection of hardware and innovation. Emphasizes curiosity, hands-on work, and real-world impact.
- **Work environment**: Remote-first with hybrid options; two US offices available. BuiltIn lists roles as “Remote Workspace” and “Hybrid”.
- **Perks**: Equity (stock options) offered. The company values thoughtful engineering and believes better power delivery can unlock new computing possibilities.
- **Engineering culture**: Deep technical challenges in analog/mixed-signal IC design, magnetic materials, system integration, and software. Opportunities to work with industry veterans and shape a groundbreaking product from early stage.

## Sources
1. [powerlatticeinc.com](https://powerlatticeinc.com/)
2. [powerlatticeinc.com/about](https://powerlatticeinc.com/about)
3. [powerlatticeinc.com/careers](https://powerlatticeinc.com/careers)
4. [builtin.com](https://builtin.com/company/powerlattice-inc)
5. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/powerlattice)

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