---
title: 'Senior or Staff Embedded Software Engineer at Powerlattice Technologies Inc.'
canonical: 'https://feeny.ai/job/senior-or-staff-embedded-software-engineer-powerlattice-technologies-inc-46d0aa7tqa28'
type: 'job'
last_seen: '2026-11-02'
---

# Senior or Staff Embedded Software Engineer at Powerlattice Technologies Inc.

- **Company:** Powerlattice Technologies Inc.
- **Location:** Chandler, AZ
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-10-16
- **Last confirmed live:** 2026-11-02
- **Apply:** https://jobs.ashbyhq.com/powerlattice/05b99d2d-47c1-42aa-b624-986d9ba9fe65

## Job description

Senior/Staff Embedded Software Engineer Reports to SVP Systems and Applications

## About Us

Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.

## About the Role

We are seeking a Senior/Staff Embedded Software Engineer who is excited to work at the intersection of firmware, automation, and silicon validation for next-generation Power Delivery Chiplets. In this role, you will build both embedded firmware (C on microcontrollers) and scalable Python-based validation infrastructure that directly impacts product quality and time-to-market. You will have the opportunity to own critical pieces of the validation stack—from low-level firmware controlling hardware platforms to high-level automation frameworks, data systems, and customer-facing debug tools. The role offers broad exposure to silicon bring-up, lab automation, and system-level debugging, making it ideal for engineers who want to deepen their expertise across both embedded systems and software infrastructure. As part of a highly collaborative environment, you’ll work closely with hardware, firmware, and silicon design teams, gaining hands-on experience with real-world power management systems and complex hardware interfaces. This role provides strong opportunities to grow into technical leadership, drive architecture decisions, and shape the validation ecosystem for future products.

## Key Responsibilities

- Design and implement Python-based validation frameworks, drivers, and automation tools
- Build and maintain scalable validation infrastructure, including regression systems
- Design device drivers, board-support packages, hardware interfaces, and low-level firmware
- Develop GUIs and tools for customer debug and evaluation kits
- Create and maintain databases for test logs, results, and analysis
- Debug system-level issues across firmware, software, and hardware interfaces
- Collaborate with hardware, validation, and silicon teams during bring-up and testing
- Develop embedded firmware in C for microcontrollers

## Qualifications

This role is onsite based in Chandler, AZ

- B.S or M.S. in electrical engineering or related fields
- 7+ years of bring-up/embedded firmware level SW development experience
- Strong Python skills for automation, scripting, and test framework development
- Experience with embedded system bring-up and debugging
- Familiarity with communication interfaces: I2C, SPI, I3C, JTAG
- Experience automating and controlling lab instruments (DMMs, Oscilloscopes, Power supplies, etc.)
- Solid understanding of embedded systems fundamentals (interrupts, peripherals, timing, etc.)
- Experience with databases for validation data management
- Experience developing GUI applications

## Preferred Qualifications

- Experience in one or more areas such as wireless, networking, motor control, power management, sensors, security, bootloaders, or high-performance compute
- Silicon bring-up experience
- Firmware programming and debug
- Manufacturing deployment and debug experience
- Ability to read schematics and support board-level debug (analog/digital)

## Compensation & Benefits

Anticipated annual base salary: $130,000 - $190,000

- Competitive salary, stock option grant and benefits package
- Health, dental, vision, 401(k), etc.

## About Powerlattice Technologies Inc.

## Company Overview
- **One-liner**: PowerLattice reimagines power delivery for next-generation AI accelerators with the industry’s first power delivery chiplet, integrating voltage regulation directly into the processor package to break the AI power wall.
- **Entity Type**: Private (raised $25M in funding; stage not publicly specified)
- **Headquarters**: United States (specific city not publicly disclosed; offices in two US locations)
- **Founded**: Year not publicly available
- **Founders**: Dr. Peng Zou, Gang Ren, Sujith Dermal

## Core Business
- Primary industry: Semiconductor power delivery for AI accelerators, GPUs, and data-center processors
- Target customers: B2B – data center operators, AI hardware manufacturers, SoC designers
- Mission: “Reimagining power delivery for next-generation AI accelerators” by tightly integrating power and compute to achieve breakthrough performance, efficiency, and scalability.

## Products & Services
- **[Power Delivery Chiplet (Rainier micro-IVR architecture)]**: A monolithic chiplet that combines miniaturized on-die magnetic inductors, advanced control circuits, and a programmable software layer. It delivers voltage regulation directly inside the processor package, enabling 2-3X performance per watt, >50% reduction in power loss, and significantly extended system lifetime. Hardware product (chiplet) with software configurability.

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Total funding of $25M (announced on company website)
- **Notable Investors/Partners**: Investors include Steve Fu; board of directors includes Pat Gelsinger (former Intel CEO). Additional partners/backers not publicly detailed.
- **Growth Signals**: Early-stage company with a small team (10–20 employees per conflicting reports from BuiltIn); first-of-its-kind product targeting the urgent “power wall” problem in AI data centers; founders bring deep experience from Qualcomm, NUVIA, Intel, Huawei, and other top semiconductor firms.

## Competitive Advantages
- **On-die magnetic inductors** – miniaturized proprietary inductors integrated at the chip level, enabling tight coupling between power and compute.
- **Chiplet architecture** – scalable, configurable, and adaptable to any SoC power topology; can be embedded in substrates or interposers.
- **Order-of-magnitude reduction in power noise** and >50% reduction in effective compute power needs.
- **Performance uplift** – under fixed data center power budgets, translates into 2X or more raw performance uplift.
- **Founding team’s deep domain expertise** in power management, IVR, and high-volume IC design for tier-one customers (Apple, Samsung, Amazon).

## Strategic Focus
- Current priority: Productizing the power delivery chiplet and achieving design wins with major AI accelerator and GPU customers.
- Long-term direction: Scaling the chiplet architecture for next-generation data-center processors and expanding into broader high-performance computing markets.
- Focus on breaking the “power wall” that limits AI compute density and data center efficiency.

## Why Work Here
- **Culture**: Small, focused team working on hard problems at the intersection of hardware and innovation. Emphasizes curiosity, hands-on work, and real-world impact.
- **Work environment**: Remote-first with hybrid options; two US offices available. BuiltIn lists roles as “Remote Workspace” and “Hybrid”.
- **Perks**: Equity (stock options) offered. The company values thoughtful engineering and believes better power delivery can unlock new computing possibilities.
- **Engineering culture**: Deep technical challenges in analog/mixed-signal IC design, magnetic materials, system integration, and software. Opportunities to work with industry veterans and shape a groundbreaking product from early stage.

## Sources
1. [powerlatticeinc.com](https://powerlatticeinc.com/)
2. [powerlatticeinc.com/about](https://powerlatticeinc.com/about)
3. [powerlatticeinc.com/careers](https://powerlatticeinc.com/careers)
4. [builtin.com](https://builtin.com/company/powerlattice-inc)
5. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/powerlattice)

## Other roles at Powerlattice Technologies Inc.

- [Senior or Staff Design Verification Engineer](https://feeny.ai/job/senior-or-staff-design-verification-engineer-powerlattice-technologies-inc-hq-vx9qh10txfcw) — HQ / Vancouver, Canada
- [Applications Engineer](https://feeny.ai/job/applications-engineer-powerlattice-technologies-inc-chandler-j622nx343qje) — Chandler, AZ
- [Technical Program Manager - Silicon Development](https://feeny.ai/job/technical-program-manager-silicon-development-powerlattice-technologies-inc-hq-gc6h651g9nrf) — HQ / Vancouver, Canada
- [Senior Digital Design Engineer](https://feeny.ai/job/senior-digital-design-engineer-powerlattice-technologies-inc-chandler-0kmj9dmzjxj1) — Chandler, AZ
- [Sr. Field Applications Engineer - Power Delivery](https://feeny.ai/job/sr-field-applications-engineer-power-delivery-powerlattice-technologies-inc-jff9zvs9n5kh) — Silicon Valley, CA
- [Senior/Staff Analog IC Design Engineer](https://feeny.ai/job/senior-staff-analog-ic-design-engineer-powerlattice-technologies-inc-hq-am0zm00an62v) — HQ / Vancouver, Canada
- [Senior or Staff Hardware Design Engineer](https://feeny.ai/job/senior-or-staff-hardware-design-engineer-powerlattice-technologies-inc-chandler-ctnc8vpgay2h) — Chandler, AZ