---
title: 'Senior or Staff Hardware Design Engineer at Powerlattice Technologies Inc.'
canonical: 'https://feeny.ai/job/senior-or-staff-hardware-design-engineer-powerlattice-technologies-inc-chandler-ctnc8vpgay2h'
type: 'job'
last_seen: '2026-09-07'
---

# Senior or Staff Hardware Design Engineer at Powerlattice Technologies Inc.

- **Company:** Powerlattice Technologies Inc.
- **Location:** Chandler, AZ
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-07-09
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.ashbyhq.com/powerlattice/98f12c83-3ef2-4249-a95c-a0a1dffa9942

## Job description

## About Us

Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.

## About the Role

We are seeking a Senior or Staff Hardware Design Engineer for developing hardware system for Powerlattice’s internal usages and collaborating Powerlattice’s customers on AI/Datacenter motherboard design to enable the adoption Powerlattice’s power chiplets. This individual is responsible for end-end hardware lifecycle, from initial schematic entry to complex PCB design and system bring-up. The ideal candidate combines deep system design expertise with strong cross-functional leadership skills and a proven record of delivering complex hardware systems for data center or enterprise markets.

## Key Responsibilities

- Define and drive overall hardware system architecture and top-level specifications.
- Lead hardware system design and system integration.
- Perform high-level feasibility analysis and risk assessment.
- Review and approve hardware designs to ensure architectural alignment.
- Drive system bring-up strategy and debug execution.
- Perform hardware system design.
- Conduct schematic design, simulation, analysis, and optimization to meet performance targets.
- Provide PCB layout guidance and collaborate closely with PCB layout engineers to ensure design intent is met.
- Collaborate with PI/SI engineer to ensure the proper PDN performance.
- Participate in design reviews and contribute to design documentation.
- Participate in silicon bring-up, characterization, and debugging.
- Follow best practices for hardware system design, verification, and signoff.

## Qualifications

This role is onsite based in Chandler, AZ

- M.S. or Ph.D. in electrical engineering or related fields.
- 5+ years of hands-on hardware system design experience.
- Proven experience as a technical lead or system lead.
- Experience in working with supply chain vendors.
- Demonstrated leadership and mentorship capabilities.

## Preferred Qualifications

- Experience in server motherboard design.
- Familiarity with power delivery design and component choice for high performance server system.
- Good communication skills and ability to work in a collaborative team environment.

## Compensation & Benefits

Anticipated annual base salary for Member of Technical Staff: $150,000 - $200,000

- Stock option grant and benefits package
- Comprehensive benefits package including health, dental, vision, and 401(k)

## About Powerlattice Technologies Inc.

## Company Overview
- **One-liner**: PowerLattice reimagines power delivery for next-generation AI accelerators with the industry’s first power delivery chiplet, integrating voltage regulation directly into the processor package to break the AI power wall.
- **Entity Type**: Private (raised $25M in funding; stage not publicly specified)
- **Headquarters**: United States (specific city not publicly disclosed; offices in two US locations)
- **Founded**: Year not publicly available
- **Founders**: Dr. Peng Zou, Gang Ren, Sujith Dermal

## Core Business
- Primary industry: Semiconductor power delivery for AI accelerators, GPUs, and data-center processors
- Target customers: B2B – data center operators, AI hardware manufacturers, SoC designers
- Mission: “Reimagining power delivery for next-generation AI accelerators” by tightly integrating power and compute to achieve breakthrough performance, efficiency, and scalability.

## Products & Services
- **[Power Delivery Chiplet (Rainier micro-IVR architecture)]**: A monolithic chiplet that combines miniaturized on-die magnetic inductors, advanced control circuits, and a programmable software layer. It delivers voltage regulation directly inside the processor package, enabling 2-3X performance per watt, >50% reduction in power loss, and significantly extended system lifetime. Hardware product (chiplet) with software configurability.

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Total funding of $25M (announced on company website)
- **Notable Investors/Partners**: Investors include Steve Fu; board of directors includes Pat Gelsinger (former Intel CEO). Additional partners/backers not publicly detailed.
- **Growth Signals**: Early-stage company with a small team (10–20 employees per conflicting reports from BuiltIn); first-of-its-kind product targeting the urgent “power wall” problem in AI data centers; founders bring deep experience from Qualcomm, NUVIA, Intel, Huawei, and other top semiconductor firms.

## Competitive Advantages
- **On-die magnetic inductors** – miniaturized proprietary inductors integrated at the chip level, enabling tight coupling between power and compute.
- **Chiplet architecture** – scalable, configurable, and adaptable to any SoC power topology; can be embedded in substrates or interposers.
- **Order-of-magnitude reduction in power noise** and >50% reduction in effective compute power needs.
- **Performance uplift** – under fixed data center power budgets, translates into 2X or more raw performance uplift.
- **Founding team’s deep domain expertise** in power management, IVR, and high-volume IC design for tier-one customers (Apple, Samsung, Amazon).

## Strategic Focus
- Current priority: Productizing the power delivery chiplet and achieving design wins with major AI accelerator and GPU customers.
- Long-term direction: Scaling the chiplet architecture for next-generation data-center processors and expanding into broader high-performance computing markets.
- Focus on breaking the “power wall” that limits AI compute density and data center efficiency.

## Why Work Here
- **Culture**: Small, focused team working on hard problems at the intersection of hardware and innovation. Emphasizes curiosity, hands-on work, and real-world impact.
- **Work environment**: Remote-first with hybrid options; two US offices available. BuiltIn lists roles as “Remote Workspace” and “Hybrid”.
- **Perks**: Equity (stock options) offered. The company values thoughtful engineering and believes better power delivery can unlock new computing possibilities.
- **Engineering culture**: Deep technical challenges in analog/mixed-signal IC design, magnetic materials, system integration, and software. Opportunities to work with industry veterans and shape a groundbreaking product from early stage.

## Sources
1. [powerlatticeinc.com](https://powerlatticeinc.com/)
2. [powerlatticeinc.com/about](https://powerlatticeinc.com/about)
3. [powerlatticeinc.com/careers](https://powerlatticeinc.com/careers)
4. [builtin.com](https://builtin.com/company/powerlattice-inc)
5. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/powerlattice)

## Other roles at Powerlattice Technologies Inc.

- [Technical Program Manager](https://feeny.ai/job/technical-program-manager-powerlattice-technologies-inc-hq-vancouver-canada-gc6h651g9nrf) — HQ / Vancouver, Canada
- [Senior Digital Design Engineer](https://feeny.ai/job/senior-digital-design-engineer-powerlattice-technologies-inc-chandler-0kmj9dmzjxj1) — Chandler, AZ
- [Validation Engineering Lead](https://feeny.ai/job/validation-engineering-lead-powerlattice-technologies-inc-chandler-b7wkpc0tz8bh) — Chandler, AZ
- [Sr. Field Applications Engineer - Power Delivery](https://feeny.ai/job/sr-field-applications-engineer-power-delivery-powerlattice-technologies-inc-jff9zvs9n5kh) — Silicon Valley, CA
- [Senior/Staff Silicon Quality & Reliability Engineer](https://feeny.ai/job/senior-staff-silicon-quality-reliability-engineer-powerlattice-technologies-inc-kpa4nbwdn1wt) — Chandler, AZ
- [Power Delivery Solution Architect](https://feeny.ai/job/power-delivery-solution-architect-powerlattice-technologies-inc-chandler-jgqstzr686t5) — Chandler, AZ
- [Senior/Staff Analog IC Design Engineer](https://feeny.ai/job/senior-staff-analog-ic-design-engineer-powerlattice-technologies-inc-hq-am0zm00an62v) — HQ / Vancouver, Canada