---
title: 'Senior PD Engineer: Synthesis & STA at EnCharge AI'
canonical: 'https://feeny.ai/job/senior-pd-engineer-synthesis-sta-encharge-ai-bengaluru-wfbtaq6984et'
type: 'job'
last_seen: '2026-09-12'
---

# Senior PD Engineer: Synthesis & STA at EnCharge AI

- **Company:** EnCharge AI
- **Location:** Bengaluru, India
- **Work type:** hybrid
- **Posted:** 2026-08-06
- **Last confirmed live:** 2026-09-12
- **Apply:** https://job-boards.greenhouse.io/enchargeai36/jobs/4357591009

## Job description

Job Title: Senior PD engineer : Synthesis & STA

Location:  Bangalore INDIA Hybrid / Remote

## Role Overview

We are seeking a highly skilled VLSI Synthesis & STA Specialist to take end-to-end ownership of logic synthesis and quality signoff for key blocks and sub-chips.

In this role, you will act as a critical bridge between the front-end design and back-end physical implementation teams.

You will not only drive synthesis execution to meet aggressive target frequencies but also act as an advisor to the RTL team, providing structural feedback to optimize the netlist.

This role offers a distinct growth trajectory, with the expectation to expand into adjacent physical design territories, including Place and Route (PNR) and comprehensive timing convergence.

## Key Responsibilities

- Synthesis Ownership: Drive and own the complete logic synthesis process for all designated blocks and sub-chips, ensuring optimal area, power, and performance metrics.
- Quality Signoff: Define, execute, and monitor rigorous sanity checks to achieve a high-quality, pristine Synthesis Signoff.
- RTL Collaboration: Work closely with RTL design engineers to ensure the delivery of a clean, fully linted netlist prior to handoff.
- Frequency & LOL Optimization: Deep dive into timing paths to ensure Levels of Logic (LOL) are strictly controlled and aligned with high-frequency target requirements.
- Micro-architecture Guidance: Go beyond reporting LOL violations; provide actionable RTL coding guidelines, structural recommendations, and micro-architecture inputs to help designers transform their code into a superior, synthesis-friendly netlist.
- Role Expansion: Progressively take on responsibilities in physical implementation adjacencies, actively participating in PNR execution, Static Timing Analysis (STA), and full-chip timing convergence.

Required Skills & Qualifications

- Experience: 5 to 8 years of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis.
- EDA Tools Expertise: Hands-on experience with industry-standard synthesis tools, with a strong preference for Cadence Genus. Proficiency with STA signoff tools (e.g., Tempus, PrimeTime) is also required.
- Timing & STA: Strong foundational knowledge of STA, timing constraints (SDC), delay calculation, and multi-mode multi-corner (MMMC) analysis.
- RTL & Logic Fundamentals: Deep understanding of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools.
- Netlist Optimization: Proven ability to analyze datapath architectures, identify logic bottlenecks, and recommend specific RTL changes to reduce logic depth.
- Scripting/Automation: Proficiency in Tcl, Python, or Perl for developing and maintaining synthesis flow automation and customized reporting scripts.
- Cross-Functional Communication: Excellent analytical and communication skills to effectively negotiate solutions between RTL and Physical Design teams.

## Preferred Qualifications

- Prior exposure to Place and Route (PNR) flows (e.g., Innovus, ICC2) and a solid understanding of how synthesis decisions impact physical placement and routing congestion.
- Experience with Formal Verification / Logic Equivalence Checking (LEC/Formality).

- Knowledge of advanced technology nodes (e.g., 5nm, 3nm) and their specific synthesis/timing challenges.

## About EnCharge AI

## Company Overview
- **One-liner**: EnCharge AI develops analog in-memory computing hardware and software to deliver high-efficiency, low-cost AI inference from edge devices to cloud data centers.
- **Entity Type**: Private (Series B – II stage)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2022
- **Founders**: Naveen Verma, Ph.D. (CEO) and Kailash Gopalakrishnan, Ph.D. (CTO)

## Core Business
- **Primary industry**: AI semiconductor hardware and embedded software products
- **Target customers**: B2B – enterprises deploying AI at scale, edge-device manufacturers, cloud service providers, and defense/industrial sectors
- **Mission**: Democratize advanced AI by enabling deployment beyond cloud infrastructure to local servers and mobile devices, while slashing costs and environmental impact

## Products & Services
- **Analog In-Memory Computing GPUs & Digital AI Accelerators**: Custom silicon (chiplets, ASICs) and standard-form-factor PCIe cards that perform AI inference using analog computation for orders-of-magnitude better energy efficiency and compute density.
- **Software Stack**: Seamless orchestration layer that supports on-device and cloud deployment, enabling model portability, quantization, and compiler optimizations across EnCharge’s hardware.
- **Edge-to-Cloud Platforms**: Integrated solutions for power-, space-, and cost-constrained environments, covering autonomous systems, smart devices, data center inference, and private on-premise AI.

## Market Standing
- **Valuation / Market Cap**: Not publicly disclosed
- **Key Metrics**: Annual Revenue ~$10M (LinkedIn estimate) | Total Funding $162.9M
- **Notable Investors & Partners**: Tiger Global Management (led $100M Series B, Mar 2025), Anzu Partners (led $21.7M Series A, Dec 2022), DARPA ($18.6M grant, Mar 2024), and others including corporate/institutional backers.
- **Growth Signals**: 
  - 58.6% YoY headcount growth (75 employees, as of mid-2025)
  - 39 active job openings spanning hardware, compiler, and AI architecture roles
  - 150+ patents granted, 300+ technical publications
  - Talent inflows from Intel, IBM, Cerebras, AMD, Meta, Microsoft

## Competitive Advantages
- **Analog In-Memory Computing Moa**t: A proprietary compute architecture that uses charge-domain analog circuits, validated silicon, and leverages existing semiconductor supply chains.
- **Record Efficiency**: Claims 20× higher TOPS/W, 9× higher compute density (TOPS/mm²), 10× lower total cost of ownership, and 100× lower CO₂ emissions compared to leading cloud/GPU alternatives.
- **Deep IP Portfolio**: 150+ granted patents and 300+ publications from 20+ years of foundational research by the founding team (Princeton, IBM, etc.).
- **End-to-End Solution**: Full-stack hardware and software (compiler, quantization, runtime) designed for seamless edge-to-cloud orchestration without vendor lock-in.

## Strategic Focus
- Scale production and customer deployments of their analog in-memory compute chips for high-volume edge and data center inference.
- Expand software ecosystem to support mainstream AI frameworks (PyTorch, TensorFlow, ONNX) and enable easy drop-in replacement for existing GPU-accelerated workloads.
- Deepen partnerships with defense (DARPA) and enterprise cloud providers, emphasizing data privacy, security, and sustainability.
- Double down on sustainability messaging (100× lower CO₂) to meet ESG mandates in enterprise AI procurement.

## Why Work Here
- **Mission-Driven Impact**: Opportunity to make AI accessible to the “99%” by dramatically reducing energy and cost barriers. Work is cited as a “once-in-a-lifetime” chance by leadership.
- **World-Class Team**: Colleagues include industry luminaries from Princeton, IBM, and top semiconductor houses; 57% of staff are in technical roles (engineering, research, compiler).
- **Culture of Collaboration & Innovation**: The careers page highlights integrity, growth, and collaborative problem-solving in a fast-paced startup environment.
- **Comprehensive Rewards**: Benefits package includes typical startup perks; equity likely offered given funding stage.
- **Work Policy**: Hybrid presence indicated by offices in Santa Clara, Canada, Germany, Norway, South Korea, and India. Remote flexibility likely for some roles.
- **Active Hiring**: 39 open positions across DFT, physical design, compiler engineering, and NPU architecture – strong signal of scaling and technical investment.

## Sources
1. [EnCharge AI Official Website](https://www.enchargeai.com/)
2. [EnCharge AI Careers Page](https://www.enchargeai.com/careers)
3. [EnCharge AI About Us (Leadership & Founders)](https://www.enchargeai.com/about-us)
4. [EnCharge AI LinkedIn Company Page](https://www.linkedin.com/company/encharge-ai)
5. [CB Insights Profile – EnCharge AI](https://www.cbinsights.com/company/encharge-ai)

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