---
title: 'Senior RTL Design Engineer at Efficient Computer'
canonical: 'https://feeny.ai/job/senior-rtl-design-engineer-efficient-computer-san-francisco-bay-area-or-g455vsttm900'
type: 'job'
last_seen: '2026-10-15'
---

# Senior RTL Design Engineer at Efficient Computer

- **Company:** Efficient Computer
- **Location:** San Francisco Bay Area OR Pittsburgh PA OR Austin, TX
- **Posted:** 2026-10-14
- **Last confirmed live:** 2026-10-15
- **Apply:** https://job-boards.greenhouse.io/efficientcomputer/jobs/4452346009

## Job description

Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.

We are looking for a Senior Design Engineer to design, integrate, and sign off RTL for blocks across our power-efficient SoC: the compute fabric's on-chip interconnect and memory interfaces, low-power and always-on logic, and standard peripheral IP (RISC-V, NVM, I2S, I2C). As a hands-on individual contributor, you will take blocks from microarchitecture spec through clean, synthesis-ready RTL, working closely with architects, the design lead, DV, physical design, and firmware to tape out an industry-leading ultra-low-power SoC.

This is a unique opportunity to join a growing HW engineering org early and leave your mark on our products and processes as we move from initial product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

## Key Responsibilities

RTL Design & Integration

- Implement microarchitecture and RTL for assigned blocks in the compute fabric, on-chip networks/NoC, memory interfaces, and peripheral subsystems, working from architecture and uArch specifications.
- Integrate third-party and in-house IP (RISC-V cores, NVM controllers, SRAM wrappers, I2S/I2C/APB peripherals) at the subsystem and SoC level, including bus fabric hookup and memory-mapped register interfaces.
- Write and maintain uArch and design documentation for your blocks; present them in design reviews with architecture, DV, and physical design.

Front-End Design Flows & Sign-off

- Own block-level front-end quality: lint-clean RTL, CDC and RDC analysis with waivers reviewed and documented, and LEC between RTL and netlist.
- Run synthesis, write and maintain SDC timing constraints, and analyze STA reports; iterate on RTL to meet timing, area, and power targets.
- Drive issues to closure with physical design during timing and congestion closure.

Low-Power Design

- Implement low-power RTL per UPF intent: power domains, isolation, level shifters, retention, and fine-grained clock gating.
- Contribute to PMU and always-on (AON) logic, such as power sequencing state machines and wakeup event aggregation.
- Ensure clock-gating enables are timing-clean and CDC-correct; run RTL power analysis and act on the results.

Verification Support & Debug

- Run block-level simulations and debug failures alongside the DV team; contribute directed test scenarios for corner cases, back-pressure, and power-state transitions.
- Run and debug gate-level simulations.
- Support silicon bring-up with RTL-level debug during lab validation.

Required Qualifications & Experience

- 8-10 years of front-end digital design experience on processor, accelerator, or SoC products.
- Significant contributions to at least two tapeout cycles.
- Strong proficiency in SystemVerilog for synthesizable RTL: state machines, arbiters, FIFOs and flow control, and datapath logic.
- Hands-on experience with standard VLSI front-end flows: lint, CDC/RDC, LEC, synthesis, SDC constraints, and STA, with the ability to interpret and act on their reports.
- Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, isolation, and retention.
- Working knowledge of at least one on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL level.
- Experience with on-chip memories: SRAM wrappers, banking, and memory-mapped register interfaces.
- Comfortable running RTL simulations and debugging with waveform tools.
- Clear written and verbal communication; able to document designs and hold design reviews.

Desired Qualifications & Experience

- Experience designing or integrating on-chip networks, dataflow pipelines, or memory subsystems.
- Familiarity with NVM controller RTL (MRAM, RRAM, etc.), including ECC and program/erase sequencing.
- Experience with very low power design techniques and the RTL design choices they require.
- Understanding of parallel execution models such as dataflow, SIMD, or systolic arrays.
- Experience with RTL and gate-level power analysis tools and methodologies.
- Exposure to DFT concepts: scan insertion, ATPG, and DFT-friendly RTL coding.
- Scripting skills (Python, Tcl, Perl) to automate design flows.

We offer a competitive base salary for this role, generally ranging from $180,000 to $245,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate. Why Join Efficient?

Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.

## About Efficient Computer

## Company Overview
- **One-liner**: Efficient Computer is building the world’s most energy-efficient general-purpose processor by combining a novel Fabric architecture with an intuitive compiler, targeting edge AI, industrial automation, space/defense, and beyond.
- **Entity Type**: Private (Series A)
- **Headquarters**: Pittsburgh, Pennsylvania, United States
- **Founded**: 2022
- **Founders**: Brandon Lucia (CEO) and Nathan Beckmann (Chief Architect)

## Core Business
- Primary industry/industries: Semiconductor / Computer Hardware / AI Chips
- Target customers: B2B – OEMs and systems integrators in edge AI, industrial automation, satellite/space, automotive, defense, and consumer electronics
- Mission or purpose statement: To set a new standard for energy efficiency in general-purpose computation, enabling applications that are infeasible today due to energy constraints. [efficient.computer/about](https://www.efficient.computer/about)

## Products & Services
- **[Electron E1 Processor]**: A general-purpose processor featuring the proprietary Fabric architecture and 4MB of on-chip MRAM. It replaces von Neumann execution with a spatial dataflow model, delivering up to 1 TOPS/W and scaling from 5.4 GOPS to 21.6 GOPS. Designed for always-on AI inference at the edge. [efficient.computer/technology](https://www.efficient.computer/technology)
- **[effcc Compiler]**: A drop-in replacement for GCC/Clang that automatically extracts parallelism from C, C++, and TFLite code and maps it to the Fabric architecture. Provides ultra-fast compilation times and a GDB-compatible debugging experience. [efficient.computer/technology](https://www.efficient.computer/technology)
- **[Fabric Architecture]**: The core technology – a tiled grid of reconfigurable compute nodes that eliminates instruction fetch and decode overhead, achieving 10–100× energy efficiency gains over traditional CPUs and GPUs. [efficient.computer](https://www.efficient.computer/)

## Market Standing
- **Valuation/Market Cap**: Not disclosed (private company)
- **Key Metric**: Total Funding – $70.0M across 3 rounds (Seed and Series A)
- **Notable Investors/Partners**: Triatomic Capital (led Series A), Eclipse (led Seed round). Key advisors include Alex Hawkinson (founder of SmartThings and BrightAI). [linkedin.com/company/efficientcomputer](https://www.linkedin.com/company/efficientcomputer)
- **Growth Signals**: 
  - 46 employees (+79.4% YoY, +27 people)
  - 13,966 LinkedIn followers (+180.4% yearly growth)
  - First silicon product (Electron E1) delivered to customers in mid-2025, ramping to volume distribution in 2026
  - Customer traction in physical AI, space/defense, automotive, and consumer products

## Competitive Advantages
- **Fabric Architecture**: A fundamentally new compute paradigm that is 10–100× more energy-efficient than traditional CPUs/GPUs for general-purpose workloads, including AI inference.
- **Full Programmability**: Unlike specialized accelerators that only optimize isolated kernels, the Fabric architecture accelerates entire applications without requiring code rewrites.
- **Proven Silicon**: Two silicon implementations (Electron E0 prototype and Electron E1 product) are already in customer hands.
- **World-Class Team**: Founders and key engineers are leading computer architects from Carnegie Mellon University, with deep expertise in efficient computing.

## Strategic Focus
- Scale the Electron E1 processor into high-volume production and distribution (targeting 2026).
- Expand into multiple verticals: physical AI, industrial automation, space/satellite, defense, automotive, and consumer electronics.
- Continue developing the effcc compiler ecosystem to support more frameworks and languages.
- Grow the engineering team, particularly in physical design, verification, architecture, and software optimization.

## Why Work Here
- **Cutting-Edge Technology**: Work on a novel processor architecture that redefines energy efficiency for the AI era.
- **Strong Growth Trajectory**: The company is scaling rapidly (nearly 80% headcount growth YoY) with a clear product-market fit and customer traction.
- **Engineering-Centric Culture**: 43% of the workforce is in technical roles, with a focus on computer architecture, compiler design, and silicon engineering.
- **Compensation & Benefits**: Competitive base salaries, meaningful startup equity, 401k matching, and a choose-your-own-adventure equipment allowance. [efficient.computer/about](https://www.efficient.computer/about)
- **Work Locations**: Offices in Pittsburgh, PA; San Jose, CA; and Austin, TX. Roles are on-site/hybrid at these hubs.
- **Values-Driven**: The company emphasizes integrity, impact, and accountability. [efficient.computer/about](https://www.efficient.computer/about)
- **Open Roles (as of mid-2026)**: 7 active positions including Design Verification Manager, Hardware Infrastructure & CI/CD Engineer, Senior Product Managers (Hardware/Software), Computer Architect, and Lead Physical Design Engineer.

## Sources
1. [efficient.computer](https://www.efficient.computer/)
2. [efficient.computer/about](https://www.efficient.computer/about)
3. [efficient.computer/technology](https://www.efficient.computer/technology)
4. [linkedin.com/company/efficientcomputer](https://www.linkedin.com/company/efficientcomputer)
5. [job-boards.greenhouse.io/efficientcomputer](http://job-boards.greenhouse.io/efficientcomputer)

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