---
title: 'Senior/Staff Design for Test Engineer at OLIX'
canonical: 'https://feeny.ai/job/senior-staff-design-for-test-engineer-olix-austin-g5wkstcyvzpa'
type: 'job'
last_seen: '2026-10-18'
---

# Senior/Staff Design for Test Engineer at OLIX

- **Company:** OLIX
- **Location:** Austin, TX
- **Compensation:** $321k
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-05-27
- **Last confirmed live:** 2026-10-18
- **Apply:** https://jobs.ashbyhq.com/olix/459699b0-a4e5-46b9-a4e6-d425a06d1106/application

**Skills:** Design for Test (DFT), ASIC Design, SoC Design, Scan Insertion, ATPG, Pattern Simulation, Fault Modeling, EDT, JTAG, IEEE 1149.1, IEEE 1687, Python, Tcl, Semiconductor Device Physics, SystemVerilog, Verilog, VHDL, 22nm Tape-out, High-speed SerDes, HBM/DDR DFT

> The Senior/Staff Design for Test Engineer takes end-to-end ownership of robust, and testable silicon for high-performance ASICs. Responsibilities include architecting DFTD strategies, verifying DFT features, optimizing test patterns, and collaborating with mixed-signal teams to ensure high yield and performance.

## Job description

## About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

## The Role

We are seeking highly skilled and motivated Senior/Staff DFT (Design for Test) Engineers with a strong focus on high-performance digital design to take end-to-end ownership of robust, testable silicon, from early test strategy definition to verified DFT implementation, pattern generation, and silicon bring-up. You will join a multidisciplinary group creating next-generation accelerators where digital, optical, and mixed-signal domains intersect. The ideal candidate will have extensive experience in the DFT of large-scale, high-volume ASICs and a passion for developing reliable, high-coverage test architectures that drive breakthrough AI hardware

## Responsibilities

- Architect, own, and implement the comprehensive Design-for-Test (DFT) strategy for complex high-throughput digital pipelines in advanced CMOS nodes, ensuring high test coverage and efficient test execution.
- Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST, ensuring adherence to industrial standards and sign-off criteria.
- Partner with the test engineering team to develop, validate, and optimize ATE-compatible test patterns (stuck-at, transition, bridging, etc.) to achieve aggressive fault coverage and maximise manufacturing yield.
- Drive RTL development (SystemVerilog / Verilog / VHDL) with a focus on DFT architecture, including synthesis constraints for test structures, and collaborate on formal and constrained-random verification of DFT logic.
- Analyse and minimise the DFT impact on power, performance, and area (PPA), implementing innovative techniques for efficient test access and execution.
- Collaborate with mixed-signal and software teams to define and optimise DFT interfaces, test modes, and firmware abstractions for test control and diagnosis.
- Mentor junior engineers, lead DFT design reviews, and champion best-practice methodologies for testability and debug across the ASIC development lifecycle.

## Skills & Experience

- 7+ years of hands‑on DFT architecture, implementation, and verification for high‑performance ASICs or SoCs, including ownership of at least one product with comprehensive DFT coverage.
- Proven success implementing and verifying advanced DFT features (e.g., Scan/ATPG, Boundary Scan, Memory BIST/Repair) on multi‑hundred‑MHz to multi‑GHz clock domains.
- Expertise with industry‑standard EDA flows: Scan insertion, ATPG, pattern simulation (gate-level), fault modeling, and diagnosis tools.
- Demonstrated proficiency with DFT flows: compression techniques, EDT, JTAG/IEEE 1149.1/1687, and managing large pattern sets.
- Proficiency using Python/Tcl scripting for DFT flow automation, pattern generation/management, and silicon debug/bring-up.
- Solid grounding in semiconductor device physics, fault models (stuck-at, transition, bridging), and yield enhancement strategies.
- Excellent communication and cross‑functional collaboration abilities; thrives in a fast‑moving, ambiguous environment.

## Nice to have

- Tape‑out experience at 22 nm or below.
- Knowledge of high-speed SerDes or HBM/DDR DFT challenges.
- Familiarity with AI/ML workloads or systolic arrays and their implications for DFT.
- Contributions to open‑source DFT tools or verification frameworks.

## Compensation & Equity

- Competitive Salary: Commensurate with your experience, skills, and location
- Equity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it
- Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office
- Retirement Benefits: Employer-contributed retirement plans to help you build long-term financial security.

Due to U.S. export control regulations, candidates’ eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.

## About OLIX

## Company Overview
- **One-liner**: OLIX, formerly known as Flux, is building a new compute paradigm using an SRAM-architecture integrated with photonics to solve the fundamental memory, energy, and speed constraints in deploying frontier AI.
- **Entity Type**: Private, Series A (raised $220M in February 2026)
- **Headquarters**: London, United Kingdom
- **Founded**: 2024
- **Founders**: James Dacombe (CEO)

## Core Business
- **Primary industry/industries**: Semiconductor Manufacturing, AI Infrastructure, Photonic Computing
- **Target customers**: Enterprise AI labs, hyperscalers, and frontier AI model developers requiring high-throughput, low-latency compute
- **Mission or purpose statement**: "Solving the most consequential problem in the deployment of frontier AI" by building infrastructure that overcomes the limits of current GPU-based memory architecture.

## Products & Services
- **OLIX Compute Platform**: A new hardware architecture combining SRAM-based compute with integrated photonics, designed to surpass HBM-based systems on throughput per megawatt and total cost of ownership (TCO), while delivering significantly better interactivity and latency than silicon-only SRAM architectures.

## Market Standing
- **Valuation**: Unicorn status; estimated $1–2.5B (latest round Feb 2026, per Dealroom)
- **Key Metric**: $220M in total funding (Series A, led by Hummingbird Ventures, with participation from Crane Venture Partners and others)
- **Notable Investors/Partners**: Hummingbird Ventures (Series A lead), Crane Venture Partners (pre-seed lead), and 4+ additional investors across seed and Series A rounds.
- **Growth Signals**: Headcount grew 420% YoY to 70 employees; operating in 6 countries (UK, US, Canada, Armenia, Romania, Germany); active job postings surged 188.9% YoY with 26 open roles as of mid-2026.

## Competitive Advantages
- **Unique photonic-SRAM architecture**: A contrarian bet that GPU-based approaches cannot simultaneously deliver high throughput and high interactivity at low cost due to physical design constraints.
- **Talent density**: Heavy hiring from top compute and AI companies (Apple, Amazon, Arm, Google, Tenstorrent).
- **First-mover in inference-era compute**: Targeting a fundamental bottleneck as frontier models require vastly more tokens per inference.

## Strategic Focus
- **Scale teams**: Aggressively hiring across engineering (ASIC/photonic design, FPGA, optics, process integration), operations, and legal in London, Austin, Toronto, Bristol, and San Francisco.
- **Prototype and productize**: Moving from architecture conception into hardware integration and manufacturing (roles include Process Integration Engineer, Opto-Mechanical Engineer, Layout Engineering Manager).
- **Transition from Flux branding**: Rebranded to OLIX in January 2026 to signal a new phase of company identity and scale.

## Why Work Here
- **In-person culture**: OLIX is an in-person company. They incentivize living within a 20-minute commute of the office with a £24,000 annual living-local bonus.
- **Compensation**: Benchmark-leading base salary, meaningful stock options (early employees build significant ownership), and workplace pension.
- **Benefits**: Comprehensive BUPA medical & dental (with Medical History Disregarded), 25 days holiday + UK bank holidays + birthday leave, meals on-site, cycle-to-work scheme, nursery scheme, visa sponsorship and relocation support.
- **Engineering environment**: M4 Mac standard (M5 Pro upgrade for engineering), on-site 3D-printing lab, noise-cancelling headphones, fully ergonomic workstation, and a culture of deep focus.
- **Impact**: "You will work with some of the best minds in photonics, systems, and compute on one of the defining problems of our era."

## Sources
1. [olix.com](https://olix.com/)
2. [olix.com/careers](https://olix.com/careers)
3. [LinkedIn - OLIX](https://www.linkedin.com/company/olix-computing)
4. [Dealroom - OLIX](https://dealroom.co/companies/olix-1/)
5. [jobs.ashbyhq.com/olix](https://jobs.ashbyhq.com/olix)

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