--- title: 'Senior Staff / Principal SOC Floorplan Lead at EnCharge AI' canonical: 'https://feeny.ai/job/senior-staff-principal-soc-floorplan-lead-encharge-ai-bengaluru-5rjzbdmx1e0r' type: 'job' last_seen: '2026-09-12' --- # Senior Staff / Principal SOC Floorplan Lead at EnCharge AI - **Company:** EnCharge AI - **Location:** Bengaluru, India - **Posted:** 2026-08-03 - **Last confirmed live:** 2026-09-12 - **Apply:** https://job-boards.greenhouse.io/enchargeai36/jobs/4343802009 ## Job description ## The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. ## Key Responsibilities - Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). - Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. - Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. - Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. - Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. - Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. - Methodology Development: Build and maintain scalable Floorplanning workflows and scripts (Tcl, Python) tailored for a lean, fast-moving start-up team. Required Skills & Qualifications - Experience: 12 + years of hands-on experience in Physical Design SoC Floor planning preferably in Datacenter domain, with at least 3 years acting as a lead or primary owner of SoC-level Floorplanning. - Domain Expertise: Proven track record of taping out large, complex chips—specifically for Data Center, Networking, or AI/Machine Learningapplications. - Start-Up Mentality: Highly driven, self-motivated, and comfortable with ambiguity. You take extreme ownership of your domain, pivot quickly when needed, and roll up your sleeves to get things done. - Technical Depth: - Deep understanding of how RTL structures and architectural decisions impact physical design PPA. - Extensive experience with bump planning, flip-chip package requirements, and die-to-package co-optimization. - Strong knowledge of analog/mixed-signal IP integration, shielding, and custom routing constraints. - Expertise with industry-standard physical design tools ( Cadence Innovus). - Education: BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. ## Preferred Qualifications - Experience with multi-die / chiplet integration (2.5D, 3D packaging, interposers, UCIe). - Strong scripting and automation skills (Tcl, Python, Perl, Makefile). - Knowledge of advanced clocking architectures (H-trees, meshes) for highly synchronous AI fabrics. ## What We Offer - Impact: The opportunity to build ground-up architecture and see your ideas taped out in cutting-edge silicon. - Equity: Competitive start-up equity packages—when the company wins, you win. - Culture: A flat, collaborative, and bureaucracy-free environment surrounded by top-tier industry veterans. ## About EnCharge AI ## Company Overview - **One-liner**: EnCharge AI develops analog in-memory computing hardware and software to deliver high-efficiency, low-cost AI inference from edge devices to cloud data centers. - **Entity Type**: Private (Series B – II stage) - **Headquarters**: Santa Clara, California, United States - **Founded**: 2022 - **Founders**: Naveen Verma, Ph.D. (CEO) and Kailash Gopalakrishnan, Ph.D. (CTO) ## Core Business - **Primary industry**: AI semiconductor hardware and embedded software products - **Target customers**: B2B – enterprises deploying AI at scale, edge-device manufacturers, cloud service providers, and defense/industrial sectors - **Mission**: Democratize advanced AI by enabling deployment beyond cloud infrastructure to local servers and mobile devices, while slashing costs and environmental impact ## Products & Services - **Analog In-Memory Computing GPUs & Digital AI Accelerators**: Custom silicon (chiplets, ASICs) and standard-form-factor PCIe cards that perform AI inference using analog computation for orders-of-magnitude better energy efficiency and compute density. - **Software Stack**: Seamless orchestration layer that supports on-device and cloud deployment, enabling model portability, quantization, and compiler optimizations across EnCharge’s hardware. - **Edge-to-Cloud Platforms**: Integrated solutions for power-, space-, and cost-constrained environments, covering autonomous systems, smart devices, data center inference, and private on-premise AI. ## Market Standing - **Valuation / Market Cap**: Not publicly disclosed - **Key Metrics**: Annual Revenue ~$10M (LinkedIn estimate) | Total Funding $162.9M - **Notable Investors & Partners**: Tiger Global Management (led $100M Series B, Mar 2025), Anzu Partners (led $21.7M Series A, Dec 2022), DARPA ($18.6M grant, Mar 2024), and others including corporate/institutional backers. - **Growth Signals**: - 58.6% YoY headcount growth (75 employees, as of mid-2025) - 39 active job openings spanning hardware, compiler, and AI architecture roles - 150+ patents granted, 300+ technical publications - Talent inflows from Intel, IBM, Cerebras, AMD, Meta, Microsoft ## Competitive Advantages - **Analog In-Memory Computing Moa**t: A proprietary compute architecture that uses charge-domain analog circuits, validated silicon, and leverages existing semiconductor supply chains. - **Record Efficiency**: Claims 20× higher TOPS/W, 9× higher compute density (TOPS/mm²), 10× lower total cost of ownership, and 100× lower CO₂ emissions compared to leading cloud/GPU alternatives. - **Deep IP Portfolio**: 150+ granted patents and 300+ publications from 20+ years of foundational research by the founding team (Princeton, IBM, etc.). - **End-to-End Solution**: Full-stack hardware and software (compiler, quantization, runtime) designed for seamless edge-to-cloud orchestration without vendor lock-in. ## Strategic Focus - Scale production and customer deployments of their analog in-memory compute chips for high-volume edge and data center inference. - Expand software ecosystem to support mainstream AI frameworks (PyTorch, TensorFlow, ONNX) and enable easy drop-in replacement for existing GPU-accelerated workloads. - Deepen partnerships with defense (DARPA) and enterprise cloud providers, emphasizing data privacy, security, and sustainability. - Double down on sustainability messaging (100× lower CO₂) to meet ESG mandates in enterprise AI procurement. ## Why Work Here - **Mission-Driven Impact**: Opportunity to make AI accessible to the “99%” by dramatically reducing energy and cost barriers. Work is cited as a “once-in-a-lifetime” chance by leadership. - **World-Class Team**: Colleagues include industry luminaries from Princeton, IBM, and top semiconductor houses; 57% of staff are in technical roles (engineering, research, compiler). - **Culture of Collaboration & Innovation**: The careers page highlights integrity, growth, and collaborative problem-solving in a fast-paced startup environment. - **Comprehensive Rewards**: Benefits package includes typical startup perks; equity likely offered given funding stage. - **Work Policy**: Hybrid presence indicated by offices in Santa Clara, Canada, Germany, Norway, South Korea, and India. Remote flexibility likely for some roles. - **Active Hiring**: 39 open positions across DFT, physical design, compiler engineering, and NPU architecture – strong signal of scaling and technical investment. ## Sources 1. [EnCharge AI Official Website](https://www.enchargeai.com/) 2. [EnCharge AI Careers Page](https://www.enchargeai.com/careers) 3. [EnCharge AI About Us (Leadership & Founders)](https://www.enchargeai.com/about-us) 4. [EnCharge AI LinkedIn Company Page](https://www.linkedin.com/company/encharge-ai) 5. [CB Insights Profile – EnCharge AI](https://www.cbinsights.com/company/encharge-ai) ## Other roles at EnCharge AI - [Staff Physical Design Engineer](https://feeny.ai/job/staff-physical-design-engineer-encharge-ai-us-vva2w6eepdbk) — Us-, Canada - [Technical Program Manager - Embedded Software](https://feeny.ai/job/technical-program-manager-embedded-software-encharge-ai-united-states-w18v49ve3s0r) — United States - [Principal Solutions Engineer](https://feeny.ai/job/principal-solutions-engineer-encharge-ai-united-states-vgghgxj68g9h) — United States - [Lead DFT Engineer](https://feeny.ai/job/lead-dft-engineer-encharge-ai-canada-united-states-q4ggksnf4q7g) — Canada / United States - [Senior PD Engineer: Synthesis & STA](https://feeny.ai/job/senior-pd-engineer-synthesis-sta-encharge-ai-bengaluru-wfbtaq6984et) — Bengaluru, India - [Staff Engineer: STA Methodology & Sign-off Lead](https://feeny.ai/job/staff-engineer-sta-methodology-sign-off-lead-encharge-ai-bengaluru-dnr9280vbw00) — Bengaluru, India - [Principal SOC Physical Verification & Integration Specialist](https://feeny.ai/job/principal-soc-physical-verification-integration-specialist-encharge-ai-bengaluru-z28meksf9r5v) — Bengaluru, India - [Staff / Senior Staff CAD & Methodology Engineer (Digital Implementation & Signoff)](https://feeny.ai/job/staff-senior-staff-cad-methodology-engineer-digital-implementation-signoff-bbfjk21sk0rk) — Bengaluru, India - [Research Engineer, AI Models](https://feeny.ai/job/research-engineer-ai-models-encharge-ai-germany-5kv1pnxdmybd) — Germany - [Research Engineer, AI Models](https://feeny.ai/job/research-engineer-ai-models-encharge-ai-india-s35hk7vzfyr3) — India