--- title: 'Senior/Staff Silicon Quality & Reliability Engineer at Powerlattice Technologies Inc.' canonical: 'https://feeny.ai/job/senior-staff-silicon-quality-reliability-engineer-powerlattice-technologies-inc-kpa4nbwdn1wt' type: 'job' last_seen: '2026-09-07' --- # Senior/Staff Silicon Quality & Reliability Engineer at Powerlattice Technologies Inc. - **Company:** Powerlattice Technologies Inc. - **Location:** Chandler, AZ - **Employment:** full-time - **Work type:** hybrid - **Posted:** 2026-08-03 - **Last confirmed live:** 2026-09-07 - **Apply:** https://jobs.ashbyhq.com/powerlattice/cb589a4c-e374-41dc-b837-eba22015effc ## Job description Hybrid requiring 3 days a week onsite in the office Reports To: Head of Engineering ## About Us Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing. ## About the Role We are seeking a highly skilled and hands-on Quality and Reliability Engineer to own company-wide quality, reliability, and design-for-reliability (DfR) initiatives. You will bridge the gap between design teams, wafer foundries, and OSAT partners. Your mission is to establish rigorous quality gates, build predictive reliability models, and mitigate risks from development through high-volume manufacturing. ## Key Responsibilities Quality & Vendor Management - Collaborate Cross-Functionally: Partner with foundries, OSATs, and internal teams to define process quality and reliability requirements. - Drive Ecosystem Partners: Manage external suppliers through test vehicle qualifications and manufacturing quality improvements before tape-out. - Monitor Quality Metrics: Oversee supplier quality, manufacturing excursions, and product return evaluations to ensure continuous improvements. Qualification & Risk Mitigation - Lead Product Qualification: Support internal product bring-ups, qualifications, and the disposition of excursion materials using risk assessments. - Develop Lifecycle Models: Plan and execute stress testing with partners to build predictive models for extrinsic and intrinsic failure mechanisms. Design & Methodology Strategy - Direct DfR Initiatives: Conduct wear out reliability assessments and guide design teams to optimize next-generation product architectures. - Standardize Quality Systems: Establish company-wide quality guidelines, qualification standards, and advanced frameworks to maximize product lifetime ## Preferred Qualifications Education & Experience - Advanced Degree: PhD or MS in Electrical Engineering, Physics, Materials Science, or a related field. - Proven Track Record: 8+ years of hands-on experience in semiconductor process, quality management, and product reliability. Technical Expertise - Quality & Reliability Physics: Deep command of semiconductor physics, acceleration models, and wear out mechanisms (TDDB, BTI, HCI, EM, SM). - Industry Standards: Direct experience with wafer-level reliability (WLR) tests, test structures, and quality standards (JEDEC, AEC-Q100, ISO 9001). - Statistical Proficiency: Expert in quality and reliability statistics (e.g., JMP), SPC charting, and failure rate calculations across the bathtub curve. - Failure Analysis: Strong knowledge of semiconductor defects, root-cause failure analysis (FA), 8D problem solving, and defect screening. - Circuit Dynamics: Solid understanding of quality degradation mechanisms in logic, memory, and analog circuits. Leadership & Soft Skills - Communication: Excellent written, verbal, and presentation skills to interface with executive leadership and external vendors. ## About Powerlattice Technologies Inc. ## Company Overview - **One-liner**: PowerLattice reimagines power delivery for next-generation AI accelerators with the industry’s first power delivery chiplet, integrating voltage regulation directly into the processor package to break the AI power wall. - **Entity Type**: Private (raised $25M in funding; stage not publicly specified) - **Headquarters**: United States (specific city not publicly disclosed; offices in two US locations) - **Founded**: Year not publicly available - **Founders**: Dr. Peng Zou, Gang Ren, Sujith Dermal ## Core Business - Primary industry: Semiconductor power delivery for AI accelerators, GPUs, and data-center processors - Target customers: B2B – data center operators, AI hardware manufacturers, SoC designers - Mission: “Reimagining power delivery for next-generation AI accelerators” by tightly integrating power and compute to achieve breakthrough performance, efficiency, and scalability. ## Products & Services - **[Power Delivery Chiplet (Rainier micro-IVR architecture)]**: A monolithic chiplet that combines miniaturized on-die magnetic inductors, advanced control circuits, and a programmable software layer. It delivers voltage regulation directly inside the processor package, enabling 2-3X performance per watt, >50% reduction in power loss, and significantly extended system lifetime. Hardware product (chiplet) with software configurability. ## Market Standing - **Valuation/Market Cap**: Not disclosed - **Key Metric**: Total funding of $25M (announced on company website) - **Notable Investors/Partners**: Investors include Steve Fu; board of directors includes Pat Gelsinger (former Intel CEO). Additional partners/backers not publicly detailed. - **Growth Signals**: Early-stage company with a small team (10–20 employees per conflicting reports from BuiltIn); first-of-its-kind product targeting the urgent “power wall” problem in AI data centers; founders bring deep experience from Qualcomm, NUVIA, Intel, Huawei, and other top semiconductor firms. ## Competitive Advantages - **On-die magnetic inductors** – miniaturized proprietary inductors integrated at the chip level, enabling tight coupling between power and compute. - **Chiplet architecture** – scalable, configurable, and adaptable to any SoC power topology; can be embedded in substrates or interposers. - **Order-of-magnitude reduction in power noise** and >50% reduction in effective compute power needs. - **Performance uplift** – under fixed data center power budgets, translates into 2X or more raw performance uplift. - **Founding team’s deep domain expertise** in power management, IVR, and high-volume IC design for tier-one customers (Apple, Samsung, Amazon). ## Strategic Focus - Current priority: Productizing the power delivery chiplet and achieving design wins with major AI accelerator and GPU customers. - Long-term direction: Scaling the chiplet architecture for next-generation data-center processors and expanding into broader high-performance computing markets. - Focus on breaking the “power wall” that limits AI compute density and data center efficiency. ## Why Work Here - **Culture**: Small, focused team working on hard problems at the intersection of hardware and innovation. Emphasizes curiosity, hands-on work, and real-world impact. - **Work environment**: Remote-first with hybrid options; two US offices available. BuiltIn lists roles as “Remote Workspace” and “Hybrid”. - **Perks**: Equity (stock options) offered. The company values thoughtful engineering and believes better power delivery can unlock new computing possibilities. - **Engineering culture**: Deep technical challenges in analog/mixed-signal IC design, magnetic materials, system integration, and software. Opportunities to work with industry veterans and shape a groundbreaking product from early stage. ## Sources 1. [powerlatticeinc.com](https://powerlatticeinc.com/) 2. [powerlatticeinc.com/about](https://powerlatticeinc.com/about) 3. [powerlatticeinc.com/careers](https://powerlatticeinc.com/careers) 4. [builtin.com](https://builtin.com/company/powerlattice-inc) 5. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/powerlattice) ## Other roles at Powerlattice Technologies Inc. - [Technical Program Manager](https://feeny.ai/job/technical-program-manager-powerlattice-technologies-inc-hq-vancouver-canada-gc6h651g9nrf) — HQ / Vancouver, Canada - [Senior Digital Design Engineer](https://feeny.ai/job/senior-digital-design-engineer-powerlattice-technologies-inc-chandler-0kmj9dmzjxj1) — Chandler, AZ - [Validation Engineering Lead](https://feeny.ai/job/validation-engineering-lead-powerlattice-technologies-inc-chandler-b7wkpc0tz8bh) — Chandler, AZ - [Sr. Field Applications Engineer - Power Delivery](https://feeny.ai/job/sr-field-applications-engineer-power-delivery-powerlattice-technologies-inc-jff9zvs9n5kh) — Silicon Valley, CA - [Power Delivery Solution Architect](https://feeny.ai/job/power-delivery-solution-architect-powerlattice-technologies-inc-chandler-jgqstzr686t5) — Chandler, AZ - [Senior/Staff Analog IC Design Engineer](https://feeny.ai/job/senior-staff-analog-ic-design-engineer-powerlattice-technologies-inc-hq-am0zm00an62v) — HQ / Vancouver, Canada - [Senior or Staff Hardware Design Engineer](https://feeny.ai/job/senior-or-staff-hardware-design-engineer-powerlattice-technologies-inc-chandler-ctnc8vpgay2h) — Chandler, AZ