---
title: 'Senior Staff Software Engineer, Linux Kernel at Efficient Computer'
canonical: 'https://feeny.ai/job/senior-staff-software-engineer-linux-kernel-efficient-computer-san-francisco-r05772pqmge3'
type: 'job'
last_seen: '2026-10-15'
---

# Senior Staff Software Engineer, Linux Kernel at Efficient Computer

- **Company:** Efficient Computer
- **Location:** San Francisco Bay Area OR Pittsburgh, PA
- **Posted:** 2026-10-06
- **Last confirmed live:** 2026-10-15
- **Apply:** https://job-boards.greenhouse.io/efficientcomputer/jobs/4434739009

## Job description

Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.

Efficient Computer is building the next generation of energy efficient, general-purpose processors designed around the Fabric architecture,  a novel spatial dataflow design spun out from decades of fundamental SOC research at CMU.

We are looking for a Senior Staff  Linux Kernel Driver Engineer to own the kernel-mode driver that brings our Fabric to life.  You will bring up new silicon from the very first boot, often before the silicon exists, working in QEMU, functional simulation, emulation, and FPGA environments to make sure our runtime software layers work on day one.

This is a key role for the System Software team:  you will work closely with architecture, micro-architecture, verification and compiler teams during pre-silicon development and bring-up.

## Key Responsibilities

Own the Kernel Driver

- Design, implement, and maintain the Linux kernel-mode driver for the Fabric accelerator.  This includes device discovery and probe, MMIO register interfaces, interrupt handling, command and completion queue management, power management, firmware, chip diagnostics, logging and device health, as well as abstracting the user-space ABI with a HAL that the runtime depends on.
- Define how custom hardware accelerators are exposed to Linux: ioctl and sysfs interfaces, and the submission and synchronization model between application cores and the Fabric.
- Keep the driver clean, upstreamable in style, and portable across kernel and device versions.
- Implement the unified memory model between ARM cores and the Fabric accelerator.
- Own SMMU (IOMMU) integration: stream and context configuration, tensor pool allocation,  page table management, stage-1 and stage-2 translation, shared virtual addressing, and fault handling.

Drive Pre-Silicon Bringup and Platform Enablement

- Build and maintain QEMU device models and board definitions for the Fabric and its SoC so that the kernel, driver, and runtime can be developed and tested before silicon.
- Own the Linux boot path on new platforms: boot firmware handoff, device tree, kernel configuration, early console, and root filesystem, from the first boot in emulation through FPGA prototypes to production silicon.
- Lead kernel-side bring up on first silicon: validating MMIO map, interrupts, clocks, resets, and memory against the hardware specification, and turning what you find into bug reports and design feedback for the hardware team.
- Be the go-to engineer for kernel debugging across the stack: crash dumps, KGDB and JTAG, ftrace and perf, lockdep and KASAN, and the hard-to-reproduce hangs and memory corruptions that only show up on real hardware.
- Establish kernel-level test coverage, including driver unit tests, emulation-based regression suites, and hardware-in-the-loop validation.

Required Qualifications

- B.S. in Electrical/Computer Engineering, Computer Science, or equivalent; M.S. a plus.
- 7+ years of systems software experience, including significant hands-on Linux kernel-mode driver development for complex devices (accelerators, GPUs, NPUs, networking, or storage).
- Deep understanding of Linux kernel memory management, including cache coherence, IOMMU/SMMU configuration, and unified or shared virtual memory between CPU and accelerators.
- Hands-on experience with QEMU, emulation, or simulation environments, including writing or extending device models and board definitions.
- Experience with pre-silicon hardware bring up and first-silicon enablement, working from hardware specifications and register maps before the platform is stable.
- Experience designing runtime interfaces between kernel and user space: ABI and HAL design, synchronization, memory sharing, and error handling.
- Strong kernel debugging skills across crash analysis, tracing, hardware debuggers, and race and memory-corruption diagnosis.
- Fluency with memory-mapped I/O: register-level programming, ordering and barrier semantics, and interrupt handling.
- Experience interfacing custom hardware accelerators to Linux.
- Strong experience with ARM cores and the ARM architecture (AArch64, exception levels, GIC, SMMU, cache and memory attributes).
- Solid understanding of the Linux boot flow: boot firmware, device tree, kernel initialization, and early platform enablement.
- Expert C and strong scripting skills; comfortable working with AI-assisted development tools for code, analysis, and debugging.

Desired Qualifications

- Experience with FPGA prototyping and hardware emulation platforms (Palladium, Zebu, Veloce, or similar).
- Knowledge of dataflow, spatial, or other novel compute architectures, and of how compilers and runtimes target them.
- Experience on a first-generation silicon product, where the software stack and the hardware matured together.
- Experience working on a CUDA, ROCm, or other language runtime software stack.

We offer a competitive base salary for this role, generally ranging from $220,000 to $270,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate. Why Join Efficient?

Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.

## About Efficient Computer

## Company Overview
- **One-liner**: Efficient Computer is building the world’s most energy-efficient general-purpose processor by combining a novel Fabric architecture with an intuitive compiler, targeting edge AI, industrial automation, space/defense, and beyond.
- **Entity Type**: Private (Series A)
- **Headquarters**: Pittsburgh, Pennsylvania, United States
- **Founded**: 2022
- **Founders**: Brandon Lucia (CEO) and Nathan Beckmann (Chief Architect)

## Core Business
- Primary industry/industries: Semiconductor / Computer Hardware / AI Chips
- Target customers: B2B – OEMs and systems integrators in edge AI, industrial automation, satellite/space, automotive, defense, and consumer electronics
- Mission or purpose statement: To set a new standard for energy efficiency in general-purpose computation, enabling applications that are infeasible today due to energy constraints. [efficient.computer/about](https://www.efficient.computer/about)

## Products & Services
- **[Electron E1 Processor]**: A general-purpose processor featuring the proprietary Fabric architecture and 4MB of on-chip MRAM. It replaces von Neumann execution with a spatial dataflow model, delivering up to 1 TOPS/W and scaling from 5.4 GOPS to 21.6 GOPS. Designed for always-on AI inference at the edge. [efficient.computer/technology](https://www.efficient.computer/technology)
- **[effcc Compiler]**: A drop-in replacement for GCC/Clang that automatically extracts parallelism from C, C++, and TFLite code and maps it to the Fabric architecture. Provides ultra-fast compilation times and a GDB-compatible debugging experience. [efficient.computer/technology](https://www.efficient.computer/technology)
- **[Fabric Architecture]**: The core technology – a tiled grid of reconfigurable compute nodes that eliminates instruction fetch and decode overhead, achieving 10–100× energy efficiency gains over traditional CPUs and GPUs. [efficient.computer](https://www.efficient.computer/)

## Market Standing
- **Valuation/Market Cap**: Not disclosed (private company)
- **Key Metric**: Total Funding – $70.0M across 3 rounds (Seed and Series A)
- **Notable Investors/Partners**: Triatomic Capital (led Series A), Eclipse (led Seed round). Key advisors include Alex Hawkinson (founder of SmartThings and BrightAI). [linkedin.com/company/efficientcomputer](https://www.linkedin.com/company/efficientcomputer)
- **Growth Signals**: 
  - 46 employees (+79.4% YoY, +27 people)
  - 13,966 LinkedIn followers (+180.4% yearly growth)
  - First silicon product (Electron E1) delivered to customers in mid-2025, ramping to volume distribution in 2026
  - Customer traction in physical AI, space/defense, automotive, and consumer products

## Competitive Advantages
- **Fabric Architecture**: A fundamentally new compute paradigm that is 10–100× more energy-efficient than traditional CPUs/GPUs for general-purpose workloads, including AI inference.
- **Full Programmability**: Unlike specialized accelerators that only optimize isolated kernels, the Fabric architecture accelerates entire applications without requiring code rewrites.
- **Proven Silicon**: Two silicon implementations (Electron E0 prototype and Electron E1 product) are already in customer hands.
- **World-Class Team**: Founders and key engineers are leading computer architects from Carnegie Mellon University, with deep expertise in efficient computing.

## Strategic Focus
- Scale the Electron E1 processor into high-volume production and distribution (targeting 2026).
- Expand into multiple verticals: physical AI, industrial automation, space/satellite, defense, automotive, and consumer electronics.
- Continue developing the effcc compiler ecosystem to support more frameworks and languages.
- Grow the engineering team, particularly in physical design, verification, architecture, and software optimization.

## Why Work Here
- **Cutting-Edge Technology**: Work on a novel processor architecture that redefines energy efficiency for the AI era.
- **Strong Growth Trajectory**: The company is scaling rapidly (nearly 80% headcount growth YoY) with a clear product-market fit and customer traction.
- **Engineering-Centric Culture**: 43% of the workforce is in technical roles, with a focus on computer architecture, compiler design, and silicon engineering.
- **Compensation & Benefits**: Competitive base salaries, meaningful startup equity, 401k matching, and a choose-your-own-adventure equipment allowance. [efficient.computer/about](https://www.efficient.computer/about)
- **Work Locations**: Offices in Pittsburgh, PA; San Jose, CA; and Austin, TX. Roles are on-site/hybrid at these hubs.
- **Values-Driven**: The company emphasizes integrity, impact, and accountability. [efficient.computer/about](https://www.efficient.computer/about)
- **Open Roles (as of mid-2026)**: 7 active positions including Design Verification Manager, Hardware Infrastructure & CI/CD Engineer, Senior Product Managers (Hardware/Software), Computer Architect, and Lead Physical Design Engineer.

## Sources
1. [efficient.computer](https://www.efficient.computer/)
2. [efficient.computer/about](https://www.efficient.computer/about)
3. [efficient.computer/technology](https://www.efficient.computer/technology)
4. [linkedin.com/company/efficientcomputer](https://www.linkedin.com/company/efficientcomputer)
5. [job-boards.greenhouse.io/efficientcomputer](http://job-boards.greenhouse.io/efficientcomputer)

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