--- title: 'Senior System Validation Engineer at Astera Labs' canonical: 'https://feeny.ai/job/senior-system-validation-engineer-astera-labs-tel-aviv-yafo-7grrjpfc0rdd' type: 'job' last_seen: '2026-09-18' --- # Senior System Validation Engineer at Astera Labs - **Company:** Astera Labs - **Location:** Tel Aviv-Yafo, Israel - **Posted:** 2026-09-16 - **Last confirmed live:** 2026-09-18 - **Apply:** https://job-boards.greenhouse.io/asteralabs/jobs/4734437005 ## Job description Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/). Senior System Validation Engineer Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ technologies with the company’s COSMOS software suite to enable scalable, high-performance AI infrastructure. Discover more at [www.asteralabs.com](https://nam02.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.asteralabs.com%2F&data=05%7C02%7CGili.Neuman%40asteralabs.com%7C9c22a8a76b544a0127ed08df12f3fa29%7Cf47c88fd08a94016b4883f361c03ff2e%7C0%7C0%7C639250511223132752%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=E5o%2F2Jk1hYGW7AkhtrbaiF%2FbthbTmKer1cJS8vWE9eQ%3D&reserved=0). Overview: Astera Labs is seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications. In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues. This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed. Key Responsibilities: - Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness. - Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions. - Develop validation tests to verify functionality, performance, stability, power, and operating margins. - Debug issues across silicon, hardware, firmware, drivers, and system software. - Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces. - Develop Python scripts and automation to improve validation coverage, regression, and test efficiency. - Analyze validation data, identify issues and trends, and drive problems to root cause and closure. - Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues. - Support the transition of new silicon from initial bring-up to a qualified, production-ready product. - Operate system platforms and laboratory equipment to support validation and debug. - Document test results, issues, root cause, and recommendations and communicate findings clearly. Basic Qualifications: - B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or a related field. - 6+ years of experience in post-silicon, system, hardware, or product validation. - Hands-on experience with SoC/silicon bring-up, functional validation, and system-level debug. - Experience developing and executing validation plans, test cases, and characterization experiments. - Strong Python scripting and test automation skills. - Strong hardware debugging, analytical, and problem-solving skills with the ability to work independently. - Experience debugging issues across hardware, firmware, and software. - Experience validating high-speed interfaces such as PCIe, Ethernet, SerDes, CXL, or DDR. - Hands-on experience working in a hardware or system validation laboratory. - Strong communication and cross-functional collaboration skills. Preferred Qualifications: - Experience with PVT validation, silicon corner testing, characterization, qualification, and margin analysis. - Experience with server, storage, networking, or AI infrastructure products. - Familiarity with PCIe/CXL architecture and high-speed SerDes technologies. - Experience with oscilloscopes, BERTs, protocol analyzers, traffic generators, or similar lab equipment. - Working knowledge of Python, firmware, Linux, and system-level software debugging. - Experience developing automated validation and regression environments. - Familiarity with Git and software development practices. - Experience with pre-silicon validation, emulation, or hardware prototyping. - Experience with system performance, throughput, latency, power, and stability testing. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. ## About Astera Labs ## Company Overview - **One-liner**: Astera Labs designs and delivers semiconductor-based connectivity solutions purpose-built to unleash the full potential of cloud and AI infrastructure. - **Entity Type**: Public (Nasdaq: ALAB) - **Headquarters**: Santa Clara, California, United States - **Founded**: 2017 - **Founders**: Jitendra Mohan, Sanjay Gajendra, Casey Morrison ## Core Business - **Primary industry**: Semiconductor manufacturing / AI infrastructure connectivity - **Target customers**: B2B, primarily hyperscale cloud providers and system OEMs (e.g., NVIDIA, AMD, Intel) - **Mission statement**: To innovate, design, and deliver semiconductor-based connectivity solutions that are purpose-built to unleash the full potential of cloud and AI infrastructure. ## Products & Services - **Aries PCIe®/CXL™ Smart DSP Retimers**: Silicon ICs, boards, and modules that digitally recover degraded high-speed signals to extend reach and enable higher PCIe/CXL data bandwidth between compute, storage, and network controllers. - **Taurus Ethernet Smart Cable Modules™**: Hardware modules that increase network connectivity bandwidth between servers and switches over copper media, removing rack-level Ethernet bottlenecks. - **Leo CXL Memory Connectivity Controllers**: ICs and boards that expand, share, and pool DRAM memory to overcome processor memory bandwidth bottlenecks for AI workloads. - **Scorpio Smart Fabric Switches**: A family of PCIe 6 fabric switches ranging from 32 to 320 lanes, including the new 320-lane Scorpio X-Series Fabric Switch for AI scale-up fabrics. - **COSMOS Software Suite**: A connectivity system management and optimization software that enables configuration, monitoring, troubleshooting, and predictive analytics for all Astera Labs products. ## Market Standing - **Market Cap**: ~$11.6 billion (as of mid-2026) - **Key Metric - Revenue**: $35 million (annual, reported) - **Key Metric - Operating Income**: $173.4 million (2025) - **Key Metric - Net Income**: $219.1 million (2025) - **Total Funding**: ~$810.75 million (pre-IPO), with Series C ($50M, led by Fidelity) and Series D ($150M, led by Fidelity) - **IPO Date**: March 20, 2024 - **Notable Investors/Partners**: Fidelity, NVIDIA, Advanced Micro Devices, Intel, major hyperscalers - **Growth Signals**: 92% YoY headcount growth (675 employees); 144 active job postings (+260% YoY); expanded Taiwan operations with a new Cloud-Scale Interop Lab in 2026; shipping millions of devices across all major hyperscalers; 300+ design wins. ## Competitive Advantages - **First-to-market innovation**: Pioneered first-to-market PCIe, Ethernet, and CXL connectivity products. - **Patented software-defined platform approach**: Differentiates via a platform that combines silicon hardware with embedded COSMOS software, enabling flexibility, observability, and predictive analytics. - **Deep hyperscaler relationships**: Trusted partner to the world’s largest cloud providers, with proven interoperability validated in their own Cloud-Scale Interop Lab. - **Broad product portfolio**: Covers PCIe retimers, Ethernet cable modules, CXL memory controllers, and fabric switches—addressing the full spectrum of AI connectivity bottlenecks. - **Strong IP and engineering talent**: 443 employees in technical roles; talent sourced from Intel (65), Marvell (37), Texas Instruments (40), AMD (22), and NVIDIA. ## Strategic Focus - **Scaling AI infrastructure**: Expanding product portfolio and global footprint (12 countries) to meet surging demand for rack-scale AI. - **Open standards leadership**: All products are grounded in open standards (PCIe, CXL, Ethernet), ensuring interoperability and broad adoption. - **Taiwan expansion**: Growing engineering presence and Interop Lab in Taiwan to strengthen integration with leading AI platform providers and system manufacturers. - **Continued innovation**: Shipping the new 320-lane Scorpio X-Series Fabric Switch and expanding the COSMOS software suite for fleet-level management and optimization. ## Why Work Here - **Culture**: Described as collaborative, ownership-driven, and focused on solving complex problems together. The company emphasizes diversity and inclusion as drivers of creativity and innovation. - **Growth**: Astera Labs supports non-linear career growth—employees can deepen expertise (“scale up”) or broaden into new areas (“scale out”). 92% YoY headcount growth signals rapid expansion and opportunity. - **Remote/Hybrid**: Not explicitly stated, but global operations across 12 countries (including India, Canada, Israel, Taiwan, Vietnam) suggest a flexible, distributed work model. - **Benefits**: Competitive medical, dental, and vision plans; flexible time off; family planning and parental leave; 401K and retirement plans. - **Engineering culture**: Strong focus on cutting-edge semiconductor and AI infrastructure technology. High concentration of senior (24%) and specialist (19%) talent. Active internship and new graduate programs. - **Employee ratings**: 4.5/5.0 on LinkedIn (124 reviews), with high marks for compensation (4.6), culture (4.4), and career development (4.4). ## Sources 1. [Astera Labs Careers Page](https://www.asteralabs.com/careers/) 2. [Astera Labs Official Website](https://www.asteralabs.com/) 3. [Astera Labs LinkedIn](https://www.linkedin.com/company/astera-labs) 4. [Astera Labs Products Page](https://www.asteralabs.com/products/) 5. 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