---
title: 'Silicon Validation Engineer, Software at Etched'
canonical: 'https://feeny.ai/job/silicon-validation-engineer-software-etched-san-jose-qhp3k9xqy5vr'
type: 'job'
last_seen: '2026-09-07'
---

# Silicon Validation Engineer, Software at Etched

- **Company:** [Etched](https://feeny.ai/companies/etched)
- **Location:** San Jose, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-09-03
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.ashbyhq.com/etched/82622c6f-9b8f-44d1-b8fc-2d4634f5abbf

## Job description

## About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a skilled and motivated Silicon Validation Firmware Engineer to develop the firmware and low-level software that validates our AI/ML accelerator ASICs across their entire Lifecycle, from pre-silicon emulation and FPGA prototyping through post-silicon bring-up, characterization, and production ramp. In this role you will build the validation firmware, test content, and automation that prove our silicon works, and you will be hands-on debugging real hardware in the lab. Your work directly enables functional correctness, performance, and reliability of our cutting-edge products.

## Key Responsibilities

- Develop and own low-level validation firmware in C/C++ that runs across emulation and physical silicon, providing test content pre-silicon and reusing it to drive post-silicon bring-up.
- Drive early bring-up of first silicon: boot, initialization, feature enablement, and debug of ASICs.
- Perform deep-dive debug of silicon issues spanning firmware, RTL, electrical, protocol, and system levels; root-cause and resolve failures.
- Build firmware infrastructure including hardware abstraction layers (HALs) and low-level device drivers for compute units, memory subsystems, and high-speed interfaces.
- Develop and extend validation automation, result-capture, and regression frameworks (CI/CD) to run validation at scale.
- Author firmware-driven test plans and define coverage metrics across IP blocks and subsystems; execute functional, performance, and stress/corner-case testing.
- Validate and characterize custom IP blocks and accelerator components on both pre- and post-silicon platforms.
- Use debug consoles and lab tooling (JTAG, UART, logic/protocol analyzers) for silicon debug and characterization.
- Collaborate closely with design, verification, architecture, DFT, and driver teams to ensure a smooth transition from pre-silicon verification to post-silicon validation, and to feed silicon issues back into revisions and firmware/driver workarounds.

You may be a good fit if you have (Must-have qualifications)

- Proficiency in C/C++ for firmware and bare-metal development, plus Python for validation automation and scripting.
- Understanding of SoC/computer architecture (CPU cores, memory subsystems, caches, interconnects).
- Solid low-level/embedded fundamentals: bootloaders, hardware abstraction layers, device drivers, register/interrupt programming, and bare-metal or RTOS environments.
- Knowledge and familiarity developing and debugging in Linux environments.
- Strong problem-solving, analytical, and cross-functional collaboration skills across hardware and software teams.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (Master's a plus).

Strong candidates may also have experience with (Nice-to-have qualifications)

- 2+ years of experience developing firmware / embedded software for ASICs or SoCs
- Hands-on experience with silicon bring-up and low-level debug (boot, initialization, root-causing failures across firmware/electrical/protocol layers).
- Experience with JTAG and debuggers (e.g., Lauterbach/GDB) and serial/UART debug consoles.
- Experience across both pre-silicon (emulation, FPGA, RTL simulation) and post-silicon (lab bring-up, characterization) environments.
- Experience with one or more high-speed interfaces: PCIe, DDR/LPDDR/HBM, SerDes, or die-to-die / chiplet interconnect.
- Experience building test/validation automation and regression frameworks (CI/CD).
- RTOS experience (FreeRTOS, Zephyr, NuttX) or RISC-V firmware development.
- Familiarity with platform/system firmware (UEFI, ACPI, BMC, BIOS).
- Ability to read RTL (Verilog/SystemVerilog) and debug in simulation.
- Hands-on lab instrumentation experience (oscilloscopes, logic/protocol analyzers, BERTs) and signal-integrity awareness.

## Benefits

- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in our office
- Unlimited compute budget subject to ROI justification

## How we’re different

Etched believes in the Bitter Lesson http://www.incompleteideas.net/IncIdeas/BitterLesson.html. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

## About Etched

## Company Overview
- **One-liner**: Etched designs and manufactures specialized ASICs (application-specific integrated circuits) that are hardwired to run transformer-based AI models, offering an order-of-magnitude improvement in inference cost and energy efficiency over general-purpose GPUs.
- **Entity Type**: Private (Series B / later stage; total raised $800M as of June 2026)
- **Headquarters**: San Jose, California, USA (also has offices in Cupertino, CA; Sacramento, CA; and small presence in Taiwan, Canada, UK, Bulgaria)
- **Founded**: 2022
- **Founders**: Gavin Uberti (CEO), Robert Wachen (President & COO), Chris Zhu (Co-Founder)

## Core Business
- **Primary industry**: AI hardware / semiconductor design / computer hardware manufacturing
- **Target customers**: Frontier AI labs, hyperscalers, and enterprises running large-scale transformer inference workloads (B2B, enterprise)
- **Mission / purpose**: Build hardware for superintelligence – specifically, the world’s most powerful servers for transformer inference.

## Products & Services
- **Sohu Chip (ASIC)**: A transformer-specific ASIC manufactured by TSMC. It burns the transformer architecture directly into silicon, eliminating the overhead of general-purpose GPUs for inference.
- **Frontier Inference Clusters**: Full-stack systems that bundle the Sohu chip with custom-designed racks, networking, and software. Customers place orders for complete systems, not just chips. Etched claims they deliver more tokens per dollar and per watt for dense models, sparse MoEs, diffusion models, and more.
- **Software Stack**: Includes compiler and runtime optimizations built by a team with deep experience (former Apache TVM developer, ex-Google TPU software lead).

## Market Standing
- **Valuation**: $5 billion post-money valuation (as of December 2025 / disclosed June 2026)
- **Key Metric**: $1 billion in contract orders (booked) for its systems; total funding of $800M (including an unannounced $500M round closed Dec 2025 led by Stripes)
- **Notable Investors**: Stripes (lead), VentureTech Alliance, Jane Street, Hudson River Trading, Two Sigma, Ribbit Capital. Angel investors include Andrej Karpathy, Geoffrey Hinton, Fei-Fei Li, Arthur Mensch, Scott Wu, Stanley Druckenmiller, Peter Thiel. Earlier backers: Positive Sum, Primary Venture Partners.
- **Growth Signals**:
  - Headcount: 258 employees (as of mid-2026), up 141% year-over-year
  - 100+ active job postings across engineering, operations, and business functions
  - $500M raise in late 2025; first chip manufactured by TSMC in 2025 and now being tested with customers
  - Talent sources include Google (21), Apple (17), NVIDIA (16), Tesla (11), Intel (10), AMD (5)

## Competitive Advantages
- **Transformer-specific architecture**: Unlike GPUs (which are general-purpose), Etched’s chip is hardwired only for transformer operations, enabling drastically lower cost and latency for today’s dominant AI model architecture.
- **Full-stack system play**: By selling entire inference clusters (chip + rack + software), Etched captures more value and delivers a turnkey solution competitive with NVIDIA’s DGX/HGX systems.
- **Deeply experienced leadership**:
  - CEO Gavin Uberti (Harvard math researcher, AI compiler expert, Apache TVM contributor)
  - President Robert Wachen (co-founded Prod AI incubator; Thiel Fellow)
  - VP of Platform (ex-NVIDIA 22 years, built HGX/DGX systems)
  - VP of Software (ex-Google DeepMind, lead TPU v1–v5 software)
  - Chief Architect Saptadeep Pal (former Auradine co-founder, chiplet expert)
  - VP of Hardware Engineering Ajat Hukkoo (ex-Cypress CTO, shipped >$1B revenue products)

## Strategic Focus
- **Scale manufacturing and customer deliveries**: With the first chip successfully fabricated, the company is now testing production systems and aims to fulfill $1B in pre-orders.
- **Expand engineering talent**: Aggressively hiring across silicon design, validation, infrastructure, optics, and software to support volume ramp.
- **Maintain technological lead**: Continue refining the ASIC for future transformer variants and MoE mixtures while building out a partner ecosystem.

## Why Work Here
- **Mission-driven, high-impact engineering**: “Building the hardware for superintelligence” – the company is solving one of the hardest problems in compute (inference efficiency) with a focused team.
- **Top-tier team and learning environment**: Colleagues from Google, NVIDIA, Apple, Tesla, Broadcom, and Intel; exposure to full-stack chip-to-system design.
- **In-office culture**: All roles are in-office (Cupertino and San Jose, CA). The company emphasizes on-site collaboration for hardware development. Notable perks are not heavily advertised, but compensation is competitive for the AI hardware space (equity-heavy).
- **Growth trajectory**: 141% headcount growth YoY, hundreds of open roles, and a $5B valuation signal strong backing and career acceleration potential.
- **Intellectual challenge**: Work on chip simulation, RTL design, system validation, or software infrastructure for cutting-edge AI inference.

## Sources
1. [etched.com/careers](https://www.etched.com/careers)
2. [builtin.com/company/etched](https://builtin.com/company/etched)
3. [linkedin.com/company/etched-ai](https://www.linkedin.com/company/etched-ai)
4. [cbinsights.com/company/etched](https://www.cbinsights.com/company/etched)
5. [techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/](https://techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/)

## Other roles at Etched

- [EE Hardware System Engineer (TW)](https://feeny.ai/job/ee-hardware-system-engineer-tw-etched-taipei-fgncym9kzy6w) — Taipei, Taiwan
- [RMA & Repair Lead](https://feeny.ai/job/rma-repair-lead-etched-san-jose-q0tmchh0yyrj) — San Jose, CA
- [Advanced Packaging SI/PI Engineer](https://feeny.ai/job/advanced-packaging-si-pi-engineer-etched-san-jose-47he7k0hp901) — San Jose, CA
- [Substrate IC Package Layout Design Engineer](https://feeny.ai/job/substrate-ic-package-layout-design-engineer-etched-san-jose-g36wmxc8ww9r) — San Jose, CA
- [ECAD Librarian](https://feeny.ai/job/ecad-librarian-etched-san-jose-0h5kvj2cxzk4) — San Jose, CA
- [Inventory Warehouse Coordinator](https://feeny.ai/job/inventory-warehouse-coordinator-etched-san-jose-49b0bs49ce57) — San Jose, CA
- [Logistics Analyst (Taiwan)](https://feeny.ai/job/logistics-analyst-taiwan-etched-taipei-5xzc094cqgzn) — Taipei, Taiwan
- [Communications](https://feeny.ai/job/communications-etched-san-jose-3f4bdr97hysp) — San Jose, CA
- [Production Finance](https://feeny.ai/job/production-finance-etched-san-jose-qfypbv9eh0ws) — San Jose, CA
- [CNC Machinist](https://feeny.ai/job/cnc-machinist-etched-san-jose-vxam0y7m1yc8) — San Jose, CA