---
title: 'SoC/ASIC Design Verification Engineer at zeroRISC'
canonical: 'https://feeny.ai/job/soc-asic-design-verification-engineer-zerorisc-boston-tn3fd3gsp3f4'
type: 'job'
last_seen: '2026-09-07'
---

# SoC/ASIC Design Verification Engineer at zeroRISC

- **Company:** zeroRISC
- **Location:** Boston, MA
- **Work type:** hybrid
- **Posted:** 2025-12-02
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.lever.co/zerorisc/b5c1cb4d-a365-4c51-8fd0-1e998801fd02

## Job description

zeroRISC

zeroRISC is redefining chip security and supply chain integrity by empowering device owners and operators in crucial sectors like silicon production, IoT, and critical infrastructure with full device ownership, control, and visibility. Led by the founders of the OpenTitan secure silicon project, zeroRISC is driving commercial adoption of high assurance software and services rooted in open silicon. Our products forge an immutable connection between hardware and software, enabling users to trust their devices no matter where they’re built or where they’re deployed.

## Role Overview

As a zeroRISC SoC/ASIC Design Verification Engineer, you will develop, verify, and maintain silicon in security-sensitive settings, including root-of-trust technology. You will elevate and solidify zeroRISC's status as the leading provider of secure silicon IP by developing essential verification collateral. You will interact directly with zeroRISC customers to understand their requirements and deliver solutions benefitting both customer and zeroRISC alike. You will participate in the whole chip design process from architecture to tapeout and silicon validation. By engaging with the world's premier open-source silicon community, you will support our mission of open secure silicon everywhere. We're looking for engineers with strong design verification skills (and a long view of secure system architecture) who are also fast, flexible learners and enthusiastic about open source.

Key Responsibilities:

- Verify ASIC/SoC functionality, performance, security, and power throughout the full chip design life cycle, from test plan definition to sign-off
- Build high quality verification environments at the chip/top and block levels following engineering best practices
- Write thorough verification documentation including test plans
- Diagnose, debug, and resolve regression failures and other errors
- Achieve coverage closure
- Ensure design functionality while upholding stringent timelines in collaboration with architecture, design, software, system, and silicon validation teams as well as engineering program managers

What We’re Looking For:

- Bachelor’s degree in Electrical Engineering or Computer Science, or a related technical field or equivalent experience
- 4 years of experience with simulation-based verification methodologies and languages such as UVM and SystemVerilog or formal verification-based techniques including industry standard tools
- Experience developing and maintaining testbenches, test cases, and verification environments for simulation-based verification or formal verification environments

Preferred Qualifications (not required):

- Master’s or PhD in Electrical Engineering or Computer Science, or a related technical field or equivalent experience
- Knowledge of security ASICs or accelerators (e.g. cryptography accelerators or GPUs)
- Knowledge of computer architecture and memory subsystem architectures
- Experience verifying low power designs
- Experience with scripting languages such as Python

Why Join Us?

- Your work will directly contribute to the development of cutting-edge security solutions, protecting critical systems in industrial and IoT environments
- As a seed-stage startup, this role offers significant opportunities for learning and career growth
- Join a close-knit, innovative team where you can learn, grow, and contribute to building something meaningful in the security space

## About zeroRISC

## Company Overview
- **One-liner**: zeroRISC builds the first commercial open-source silicon root of trust and a cloud-based security platform that lets every connected device prove what it is, who made it, and what it’s running.
- **Entity Type**: Private (Seed stage; $15M total funding across two rounds)
- **Headquarters**: Boston, Massachusetts, United States (also offices in Sunnyvale, CA; Cambridge, UK; London, UK; Bristol, UK)
- **Founded**: 2023
- **Founders**: Dom Rizzo (former OpenTitan lead at Google) and original OpenTitan team members

## Core Business
- **Primary industry**: Computer and Network Security; Open-Source Silicon / Semiconductor Security
- **Target customers**: B2B – enterprises operating data centers, ICS/OT, IoT, edge devices, and AI-datacenter infrastructure
- **Mission**: “Every device should be a trusted device.”

## Products & Services
- **Integrity Management Platform**: A drop-in, all-in-one cloud service for secure device management below the operating system. It handles provisioning, lifecycle management, and secure ownership transfer – built on open-source silicon.
- **Pavona Open-Source Silicon Ecosystem**: An ecosystem for composable secure silicon. zeroRISC is a founding member alongside Analog Devices, Meta, and Qualcomm. The platform enables open, auditable hardware trust.
- **OpenTitan-Based Commercial Root of Trust**: The first production-grade, open-source silicon root of trust, designed to be transparent and vendor-independent.

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Total funding $15M (Seed round Oct 2023: $5M led by Cambridge Angels group; Seed round June 2025: $10M led by Fontinalis Partners)
- **Notable Investors/Partners**: Cambridge Angels group, Fontinalis Partners; Partners include Analog Devices, Meta, Qualcomm (via Pavona); Board includes Zakir Durumeric (Censys co-founder) and David Gammon
- **Growth Signals**: Team of 13 employees (headcount growing); LinkedIn followers up 109.6% YoY; announced post-quantum secure boot (SPHINCS+) in 2025; Pavona launch in May 2026; active job postings up 400% year-over-year

## Competitive Advantages
- **Open-source, auditable trust stack**: Security through transparency – the hardware can be inspected by researchers, customers, and regulators, unlike proprietary alternatives.
- **End-to-end ownership**: One team designs the RTL, firmware, cloud services, and field operations – no integration gaps across fab, OSAT, and field.
- **Long-horizon commitment**: Devices provisioned today will be in the field through 2040. The company treats trust as a 15-year relationship, not a one-time feature.
- **Senior, small team**: Most engineers have shipped silicon or run security programs; hiring is slow and deliberate, enabling deep trust and high ownership.

## Strategic Focus
- **Scaling open silicon adoption** through the Pavona ecosystem, expanding the commercial root of trust to devices of all sizes.
- **Commercializing OpenTitan** for broad industry use, with a focus on data centers, critical infrastructure, and edge/IoT.
- **Post-quantum security** integration (SPHINCS+ signing) to future-proof device attestation.
- **Growing the cloud platform** (Integrity Management Platform) to handle provisioning, lifecycle, and secure ownership transfer at scale.

## Why Work Here
- **Mission-driven impact**: “Every device should be a trusted device” – work directly on foundational security for the grid, finance, transport, and AI data centers.
- **High ownership, small senior team**: Engineers own greenfield design across the full stack (RTL, embedded Rust, PKI, cloud services). The team is described as “small and senior” with a decade-scale perspective.
- **Public-by-default work**: Much of the code ships open-source – your commits and reviews are public proof of impact, building personal credibility in the security community.
- **Hybrid work model**: Roles are hybrid in Boston, MA (HQ); Bristol, UK; London, UK; and Sunnyvale, CA. Some roles may require cross-timezone collaboration.
- **Culture highlights**: Transparent milestone-driven storytelling (e.g., post-quantum progress, funding announcements), clear mission, and a “long-horizon” approach. The Built In review notes that the environment suits impact-oriented security engineers comfortable with startup pace, rigor, and risk.
- **Notable perks**: Open-source contributions, upstream OpenTitan cadence, and a culture of trusting leadership over crowd-sourced reputation.

## Sources
1. [zerorisc.com/careers](https://www.zerorisc.com/careers)
2. [jobs.lever.co/zerorisc](https://jobs.lever.co/zerorisc)
3. [zerorisc.com/mission](https://www.zerorisc.com/mission)
4. [linkedin.com/company/zerorisc](https://www.linkedin.com/company/zerorisc)
5. [builtin.com/company/zerorisc-inc/faq/workplace-perception](https://builtin.com/company/zerorisc-inc/faq/workplace-perception)

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