---
title: 'Soc Design Verification Director at Astera Labs'
canonical: 'https://feeny.ai/job/soc-design-verification-director-astera-labs-bengaluru-frzbzgag988j'
type: 'job'
last_seen: '2026-09-11'
---

# Soc Design Verification Director at Astera Labs

- **Company:** Astera Labs
- **Location:** Bengaluru, India
- **Posted:** 2026-06-24
- **Last confirmed live:** 2026-09-11
- **Apply:** https://job-boards.greenhouse.io/asteralabs/jobs/4703985005

## Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/).

Job Title: Director of SoC Design Verification

## Overview

We are seeking a seasoned Director of SoC Design Verification with 20+ years of experience to lead verification for our next-generation System-on-Chip products. This is a hands-on leadership role where you will define the SoC-level verification strategy, oversee execution across multiple IPs and subsystems, and ensure first-pass silicon success for complex designs in compute, networking, and storage domains.

## Key Responsibilities

- Own and drive the end-to-end SoC verification methodology, ensuring seamless integration of IP-level verification into system-level environments.
- Lead, mentor, and grow a diverse team of engineers, fostering technical excellence, innovation, and collaboration.
- Guide verification of complex SoC subsystems including HSIO, peripherals, interconnects, memory controllers, coherency fabrics, and system-level protocols.
- Champion advanced methodologies (UVM, formal verification, emulation, AI-augmented flows) to accelerate coverage closure and improve efficiency.
- Collaborate closely with RTL design, architecture, firmware, and validation teams to debug, refine, and optimize SoC-level verification processes.
- Represent verification in executive reviews, customer engagements, and industry forums.
- Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges.

## Qualifications

- Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
- 20+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.
- Deep expertise in SoC-level verification, including interconnect fabrics, coherency protocols, HSIO, and peripheral subsystems.
- Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.
- Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.

Required Experience

- Hands-on expertise with SoC-level verification environments, including integration of multiple IPs, HSIO, and peripherals.
- Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.
- Strong background in writing assertions, cover properties, and analyzing coverage data at both IP and SoC levels.
- Experience in developing scalable verification infrastructures to simplify and accelerate SoC-level deployments.

## Preferred Experience

- Expertise in verifying complex SoC subsystems such as NoC-based interconnects, coherency fabrics, HSIO, and memory hierarchies.
- Experience with buffering, queuing, QoS, and system-level performance analysis.
- Familiarity with emulation, FPGA prototyping, and hybrid verification flows.
- Knowledge of AI-driven verification methodologies and workforce transformation strategies.
- Experience with AI/ML accelerators, networking, automotive, data center, or high-performance computing SoCs.
- Familiarity with low-power verification methodologies and power-aware verification.

-

Why Join Us?

- Opportunity to lead cutting-edge SoC development programs.
- Influence verification strategy across next-generation products.
- Build and grow a world-class verification organization.
- Work with highly talented engineering teams on innovative technologies.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## About Astera Labs

## Company Overview
- **One-liner**: Astera Labs designs and delivers semiconductor-based connectivity solutions purpose-built to unleash the full potential of cloud and AI infrastructure.
- **Entity Type**: Public (Nasdaq: ALAB)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2017
- **Founders**: Jitendra Mohan, Sanjay Gajendra, Casey Morrison

## Core Business
- **Primary industry**: Semiconductor manufacturing / AI infrastructure connectivity
- **Target customers**: B2B, primarily hyperscale cloud providers and system OEMs (e.g., NVIDIA, AMD, Intel)
- **Mission statement**: To innovate, design, and deliver semiconductor-based connectivity solutions that are purpose-built to unleash the full potential of cloud and AI infrastructure.

## Products & Services
- **Aries PCIe®/CXL™ Smart DSP Retimers**: Silicon ICs, boards, and modules that digitally recover degraded high-speed signals to extend reach and enable higher PCIe/CXL data bandwidth between compute, storage, and network controllers.
- **Taurus Ethernet Smart Cable Modules™**: Hardware modules that increase network connectivity bandwidth between servers and switches over copper media, removing rack-level Ethernet bottlenecks.
- **Leo CXL Memory Connectivity Controllers**: ICs and boards that expand, share, and pool DRAM memory to overcome processor memory bandwidth bottlenecks for AI workloads.
- **Scorpio Smart Fabric Switches**: A family of PCIe 6 fabric switches ranging from 32 to 320 lanes, including the new 320-lane Scorpio X-Series Fabric Switch for AI scale-up fabrics.
- **COSMOS Software Suite**: A connectivity system management and optimization software that enables configuration, monitoring, troubleshooting, and predictive analytics for all Astera Labs products.

## Market Standing
- **Market Cap**: ~$11.6 billion (as of mid-2026)
- **Key Metric - Revenue**: $35 million (annual, reported)
- **Key Metric - Operating Income**: $173.4 million (2025)
- **Key Metric - Net Income**: $219.1 million (2025)
- **Total Funding**: ~$810.75 million (pre-IPO), with Series C ($50M, led by Fidelity) and Series D ($150M, led by Fidelity)
- **IPO Date**: March 20, 2024
- **Notable Investors/Partners**: Fidelity, NVIDIA, Advanced Micro Devices, Intel, major hyperscalers
- **Growth Signals**: 92% YoY headcount growth (675 employees); 144 active job postings (+260% YoY); expanded Taiwan operations with a new Cloud-Scale Interop Lab in 2026; shipping millions of devices across all major hyperscalers; 300+ design wins.

## Competitive Advantages
- **First-to-market innovation**: Pioneered first-to-market PCIe, Ethernet, and CXL connectivity products.
- **Patented software-defined platform approach**: Differentiates via a platform that combines silicon hardware with embedded COSMOS software, enabling flexibility, observability, and predictive analytics.
- **Deep hyperscaler relationships**: Trusted partner to the world’s largest cloud providers, with proven interoperability validated in their own Cloud-Scale Interop Lab.
- **Broad product portfolio**: Covers PCIe retimers, Ethernet cable modules, CXL memory controllers, and fabric switches—addressing the full spectrum of AI connectivity bottlenecks.
- **Strong IP and engineering talent**: 443 employees in technical roles; talent sourced from Intel (65), Marvell (37), Texas Instruments (40), AMD (22), and NVIDIA.

## Strategic Focus
- **Scaling AI infrastructure**: Expanding product portfolio and global footprint (12 countries) to meet surging demand for rack-scale AI.
- **Open standards leadership**: All products are grounded in open standards (PCIe, CXL, Ethernet), ensuring interoperability and broad adoption.
- **Taiwan expansion**: Growing engineering presence and Interop Lab in Taiwan to strengthen integration with leading AI platform providers and system manufacturers.
- **Continued innovation**: Shipping the new 320-lane Scorpio X-Series Fabric Switch and expanding the COSMOS software suite for fleet-level management and optimization.

## Why Work Here
- **Culture**: Described as collaborative, ownership-driven, and focused on solving complex problems together. The company emphasizes diversity and inclusion as drivers of creativity and innovation.
- **Growth**: Astera Labs supports non-linear career growth—employees can deepen expertise (“scale up”) or broaden into new areas (“scale out”). 92% YoY headcount growth signals rapid expansion and opportunity.
- **Remote/Hybrid**: Not explicitly stated, but global operations across 12 countries (including India, Canada, Israel, Taiwan, Vietnam) suggest a flexible, distributed work model.
- **Benefits**: Competitive medical, dental, and vision plans; flexible time off; family planning and parental leave; 401K and retirement plans.
- **Engineering culture**: Strong focus on cutting-edge semiconductor and AI infrastructure technology. High concentration of senior (24%) and specialist (19%) talent. Active internship and new graduate programs.
- **Employee ratings**: 4.5/5.0 on LinkedIn (124 reviews), with high marks for compensation (4.6), culture (4.4), and career development (4.4).

## Sources
1. [Astera Labs Careers Page](https://www.asteralabs.com/careers/)
2. [Astera Labs Official Website](https://www.asteralabs.com/)
3. [Astera Labs LinkedIn](https://www.linkedin.com/company/astera-labs)
4. [Astera Labs Products Page](https://www.asteralabs.com/products/)
5. [Astera Labs S-1 Filing (SEC)](https://ir.asteralabs.com/static-files/7103a4cb-aa6b-4f11-a4b0-f179cd4c5bee)

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