---
title: 'Sr. Field Applications Engineer - Power Delivery at Powerlattice Technologies Inc.'
canonical: 'https://feeny.ai/job/sr-field-applications-engineer-power-delivery-powerlattice-technologies-inc-jff9zvs9n5kh'
type: 'job'
last_seen: '2026-09-07'
---

# Sr. Field Applications Engineer - Power Delivery at Powerlattice Technologies Inc.

- **Company:** Powerlattice Technologies Inc.
- **Location:** Silicon Valley, CA
- **Employment:** full-time
- **Work type:** hybrid
- **Posted:** 2026-08-06
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.ashbyhq.com/powerlattice/30159cba-3c5e-402d-937e-70fb18b71adf

## Job description

Sr. Field Applications Engineer - Power Delivery

## About Us

Powerlattice is a well-funded semiconductor startup backed by leading Silicon Valley venture capital firms. We are developing a groundbreaking chiplet solution for a fundamental shift in how high-performance chips are powered, paving the way for the next generation of AI and advanced computing. We are the first to offer a tiny device that can be integrated into a SoC package.

## About the Role

We are seeking a Sr. Field Applications Engineer (FAE) to support customers adopting Powerlattice’s chiplet-based power delivery network (PDN) solution. This role sits at the intersection of deep technical expertise and customer engagement, serving as a critical bridge between our internal design teams and tier-one customers.

The ideal candidate is highly organized, proactive, and articulate, with the technical credibility to partner directly with customer engineering teams working on the most advanced xPU SoCs in the industry. This role offers significant opportunity for impact, ownership, and growth, contributing directly to both customer product success and Powerlattice’s commercial momentum.

This position is well suited for someone who thrives in a fast-paced startup environment, anticipates needs before they arise, and enjoys being a trusted technical advisor to customers and internal teams alike.

## Key Responsibilities

- Enable customers to design GPU/CPU SoC power solution with Powerlattice’s chiplet
- Assist customer’s PDN design optimization using Powerlattice’s design kit
- Gather customer feedback and translate insights into improvements for customer enablement and product development
- Assist customers through the full adoption lifecycle, from early modeling through physical design and system bring-up
- Maintain strict confidentiality and handle sensitive technical information with discretion
- Act as a primary technical point of contact for tier-one customers

## Qualifications

This role is Hybrid requiring 3 days a week onsite at either our Chandler, AZ (Greater Phoenix) office or San Jose, CA.

- 5+ years of experience in power integrity and/or signal integrity for high-performance SoCs
- Experience with package-level power integrity and signal integrity, including motherboard, substrates, interposers, and advanced packaging (2.5D / 3D)
- Strong debugging skills to reproduce and resolve technical issues
- Excellent written and verbal communication skills, with the ability to engage directly with customer engineering teams
- High level of professionalism, discretion, and sound technical judgment
- Comfortable working independently and proactively solving problems

Bonus Points

- Working experience at major processor or ASIC companies in the related technical area
- Proven experience as engineering or project lead in a related technical area
- Hands-on experience with electrical test methodologies and instrumentation for power or signal integrity
- Experience in advanced package technologies, e.g. CoWoS, 2.5D.5D

## Compensation & Benefits

Anticipated annual base salary for Member of Technical Staff: $150,000 - $225,000

- Stock option grant
- Comprehensive benefits package including health, dental, vision, and 401(k)

## About Powerlattice Technologies Inc.

## Company Overview
- **One-liner**: PowerLattice reimagines power delivery for next-generation AI accelerators with the industry’s first power delivery chiplet, integrating voltage regulation directly into the processor package to break the AI power wall.
- **Entity Type**: Private (raised $25M in funding; stage not publicly specified)
- **Headquarters**: United States (specific city not publicly disclosed; offices in two US locations)
- **Founded**: Year not publicly available
- **Founders**: Dr. Peng Zou, Gang Ren, Sujith Dermal

## Core Business
- Primary industry: Semiconductor power delivery for AI accelerators, GPUs, and data-center processors
- Target customers: B2B – data center operators, AI hardware manufacturers, SoC designers
- Mission: “Reimagining power delivery for next-generation AI accelerators” by tightly integrating power and compute to achieve breakthrough performance, efficiency, and scalability.

## Products & Services
- **[Power Delivery Chiplet (Rainier micro-IVR architecture)]**: A monolithic chiplet that combines miniaturized on-die magnetic inductors, advanced control circuits, and a programmable software layer. It delivers voltage regulation directly inside the processor package, enabling 2-3X performance per watt, >50% reduction in power loss, and significantly extended system lifetime. Hardware product (chiplet) with software configurability.

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Total funding of $25M (announced on company website)
- **Notable Investors/Partners**: Investors include Steve Fu; board of directors includes Pat Gelsinger (former Intel CEO). Additional partners/backers not publicly detailed.
- **Growth Signals**: Early-stage company with a small team (10–20 employees per conflicting reports from BuiltIn); first-of-its-kind product targeting the urgent “power wall” problem in AI data centers; founders bring deep experience from Qualcomm, NUVIA, Intel, Huawei, and other top semiconductor firms.

## Competitive Advantages
- **On-die magnetic inductors** – miniaturized proprietary inductors integrated at the chip level, enabling tight coupling between power and compute.
- **Chiplet architecture** – scalable, configurable, and adaptable to any SoC power topology; can be embedded in substrates or interposers.
- **Order-of-magnitude reduction in power noise** and >50% reduction in effective compute power needs.
- **Performance uplift** – under fixed data center power budgets, translates into 2X or more raw performance uplift.
- **Founding team’s deep domain expertise** in power management, IVR, and high-volume IC design for tier-one customers (Apple, Samsung, Amazon).

## Strategic Focus
- Current priority: Productizing the power delivery chiplet and achieving design wins with major AI accelerator and GPU customers.
- Long-term direction: Scaling the chiplet architecture for next-generation data-center processors and expanding into broader high-performance computing markets.
- Focus on breaking the “power wall” that limits AI compute density and data center efficiency.

## Why Work Here
- **Culture**: Small, focused team working on hard problems at the intersection of hardware and innovation. Emphasizes curiosity, hands-on work, and real-world impact.
- **Work environment**: Remote-first with hybrid options; two US offices available. BuiltIn lists roles as “Remote Workspace” and “Hybrid”.
- **Perks**: Equity (stock options) offered. The company values thoughtful engineering and believes better power delivery can unlock new computing possibilities.
- **Engineering culture**: Deep technical challenges in analog/mixed-signal IC design, magnetic materials, system integration, and software. Opportunities to work with industry veterans and shape a groundbreaking product from early stage.

## Sources
1. [powerlatticeinc.com](https://powerlatticeinc.com/)
2. [powerlatticeinc.com/about](https://powerlatticeinc.com/about)
3. [powerlatticeinc.com/careers](https://powerlatticeinc.com/careers)
4. [builtin.com](https://builtin.com/company/powerlattice-inc)
5. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/powerlattice)

## Other roles at Powerlattice Technologies Inc.

- [Technical Program Manager](https://feeny.ai/job/technical-program-manager-powerlattice-technologies-inc-hq-vancouver-canada-gc6h651g9nrf) — HQ / Vancouver, Canada
- [Senior Digital Design Engineer](https://feeny.ai/job/senior-digital-design-engineer-powerlattice-technologies-inc-chandler-0kmj9dmzjxj1) — Chandler, AZ
- [Validation Engineering Lead](https://feeny.ai/job/validation-engineering-lead-powerlattice-technologies-inc-chandler-b7wkpc0tz8bh) — Chandler, AZ
- [Senior/Staff Silicon Quality & Reliability Engineer](https://feeny.ai/job/senior-staff-silicon-quality-reliability-engineer-powerlattice-technologies-inc-kpa4nbwdn1wt) — Chandler, AZ
- [Power Delivery Solution Architect](https://feeny.ai/job/power-delivery-solution-architect-powerlattice-technologies-inc-chandler-jgqstzr686t5) — Chandler, AZ
- [Senior/Staff Analog IC Design Engineer](https://feeny.ai/job/senior-staff-analog-ic-design-engineer-powerlattice-technologies-inc-hq-am0zm00an62v) — HQ / Vancouver, Canada
- [Senior or Staff Hardware Design Engineer](https://feeny.ai/job/senior-or-staff-hardware-design-engineer-powerlattice-technologies-inc-chandler-ctnc8vpgay2h) — Chandler, AZ