---
title: 'Sr. Principal Program Manager, ASIC Design at Astera Labs'
canonical: 'https://feeny.ai/job/sr-principal-program-manager-asic-design-astera-labs-toronto-ykvke7shpk9p'
type: 'job'
last_seen: '2026-09-11'
---

# Sr. Principal Program Manager, ASIC Design at Astera Labs

- **Company:** Astera Labs
- **Location:** Toronto, Canada
- **Posted:** 2026-06-25
- **Last confirmed live:** 2026-09-11
- **Apply:** https://job-boards.greenhouse.io/asteralabs/jobs/4709339005

## Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/).

## Role Overview

As a Sr. Principal Program Manager, ASIC Design at Astera Labs, you will own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.

You will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners.

This is a high-impact role for a technical program leader who can operate in a fast-moving environment, manage ambiguity, drive accountability, and establish scalable execution practices across complex silicon development programs.

## Key Responsibilities

- Program Execution & Planning

- Lead pre-silicon execution of complex ASIC and subsystem programs from concept through tapeout.
- Own program plans, schedules, milestones, dependencies, risk registers, dashboards, and executive-level status reporting.
- Drive pre-silicon and NPD phase-gate execution from kickoff through final GDS handoff, ensuring cross-functional readiness across architecture, RTL, verification, DFT, physical design, signoff, and tapeout.

- Cross-Functional Alignment & Coordination

- Drive cross-functional alignment across architecture, RTL design, verification, emulation, DFT, synthesis, physical design, CAD, IP integration, product management, and external partners.
- Track IP delivery, PDK updates, CAD/EDA flow readiness, tool dependencies, and foundry requirements.
- Partner with Post-Silicon PM and Validation teams to absorb feedback from post silicon bring up, including bug reports and Si issues.

- Risk Management & Decision-Making

- Identify execution risks, lead risk mitigation plans, and drive trade-off decisions across scope, schedule, resources, and quality.
- Communicate program health, risks, dependencies, and decisions clearly to engineering teams, senior leaders, executives, and external partners.

- Process & Operational Excellence

- Establish scalable program management practices, operating rhythms, decision forums, documentation standards, and communication mechanisms, lead constant improvement.

## Basic Qualifications

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 10+ years of experience in ASIC/SoC development or silicon program execution, including 3+ years in technical program management, engineering program management, or technical leadership.
- Experience managing pre-silicon ASIC development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout.
- Experience with advanced process nodes and high-performance ASIC/SoC development.
- Strong understanding of ASIC development milestones from product requirements through final GDS handoff.
- Familiarity with EDA flows, CAD infrastructure, IP integration, PDK readiness, foundry requirements, and vendor dependency management.
- Experience with pre-silicon validation platforms such as simulation, emulation, FPGA prototyping, or hardware/software co-validation.
- Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and aggressive schedules.

## Preferred Qualifications

- Strong technical judgment with the ability to manage trade-offs across performance, power, area, cost, schedule, quality, and risk.
- Excellent communication, organizational, leadership, and stakeholder-management skills.
- Ability to influence without authority across global, cross-functional, and cross-cultural teams.
- Ability to operate independently in a fast-paced, ambiguous, high-growth environment.
- Experience with high-speed connectivity, SerDes, PHY, PCIe, CXL, Ethernet, networking, switching, or AI infrastructure silicon.

Salary range is CAD 195,000 to CAD 240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## About Astera Labs

## Company Overview
- **One-liner**: Astera Labs designs and delivers semiconductor-based connectivity solutions purpose-built to unleash the full potential of cloud and AI infrastructure.
- **Entity Type**: Public (Nasdaq: ALAB)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2017
- **Founders**: Jitendra Mohan, Sanjay Gajendra, Casey Morrison

## Core Business
- **Primary industry**: Semiconductor manufacturing / AI infrastructure connectivity
- **Target customers**: B2B, primarily hyperscale cloud providers and system OEMs (e.g., NVIDIA, AMD, Intel)
- **Mission statement**: To innovate, design, and deliver semiconductor-based connectivity solutions that are purpose-built to unleash the full potential of cloud and AI infrastructure.

## Products & Services
- **Aries PCIe®/CXL™ Smart DSP Retimers**: Silicon ICs, boards, and modules that digitally recover degraded high-speed signals to extend reach and enable higher PCIe/CXL data bandwidth between compute, storage, and network controllers.
- **Taurus Ethernet Smart Cable Modules™**: Hardware modules that increase network connectivity bandwidth between servers and switches over copper media, removing rack-level Ethernet bottlenecks.
- **Leo CXL Memory Connectivity Controllers**: ICs and boards that expand, share, and pool DRAM memory to overcome processor memory bandwidth bottlenecks for AI workloads.
- **Scorpio Smart Fabric Switches**: A family of PCIe 6 fabric switches ranging from 32 to 320 lanes, including the new 320-lane Scorpio X-Series Fabric Switch for AI scale-up fabrics.
- **COSMOS Software Suite**: A connectivity system management and optimization software that enables configuration, monitoring, troubleshooting, and predictive analytics for all Astera Labs products.

## Market Standing
- **Market Cap**: ~$11.6 billion (as of mid-2026)
- **Key Metric - Revenue**: $35 million (annual, reported)
- **Key Metric - Operating Income**: $173.4 million (2025)
- **Key Metric - Net Income**: $219.1 million (2025)
- **Total Funding**: ~$810.75 million (pre-IPO), with Series C ($50M, led by Fidelity) and Series D ($150M, led by Fidelity)
- **IPO Date**: March 20, 2024
- **Notable Investors/Partners**: Fidelity, NVIDIA, Advanced Micro Devices, Intel, major hyperscalers
- **Growth Signals**: 92% YoY headcount growth (675 employees); 144 active job postings (+260% YoY); expanded Taiwan operations with a new Cloud-Scale Interop Lab in 2026; shipping millions of devices across all major hyperscalers; 300+ design wins.

## Competitive Advantages
- **First-to-market innovation**: Pioneered first-to-market PCIe, Ethernet, and CXL connectivity products.
- **Patented software-defined platform approach**: Differentiates via a platform that combines silicon hardware with embedded COSMOS software, enabling flexibility, observability, and predictive analytics.
- **Deep hyperscaler relationships**: Trusted partner to the world’s largest cloud providers, with proven interoperability validated in their own Cloud-Scale Interop Lab.
- **Broad product portfolio**: Covers PCIe retimers, Ethernet cable modules, CXL memory controllers, and fabric switches—addressing the full spectrum of AI connectivity bottlenecks.
- **Strong IP and engineering talent**: 443 employees in technical roles; talent sourced from Intel (65), Marvell (37), Texas Instruments (40), AMD (22), and NVIDIA.

## Strategic Focus
- **Scaling AI infrastructure**: Expanding product portfolio and global footprint (12 countries) to meet surging demand for rack-scale AI.
- **Open standards leadership**: All products are grounded in open standards (PCIe, CXL, Ethernet), ensuring interoperability and broad adoption.
- **Taiwan expansion**: Growing engineering presence and Interop Lab in Taiwan to strengthen integration with leading AI platform providers and system manufacturers.
- **Continued innovation**: Shipping the new 320-lane Scorpio X-Series Fabric Switch and expanding the COSMOS software suite for fleet-level management and optimization.

## Why Work Here
- **Culture**: Described as collaborative, ownership-driven, and focused on solving complex problems together. The company emphasizes diversity and inclusion as drivers of creativity and innovation.
- **Growth**: Astera Labs supports non-linear career growth—employees can deepen expertise (“scale up”) or broaden into new areas (“scale out”). 92% YoY headcount growth signals rapid expansion and opportunity.
- **Remote/Hybrid**: Not explicitly stated, but global operations across 12 countries (including India, Canada, Israel, Taiwan, Vietnam) suggest a flexible, distributed work model.
- **Benefits**: Competitive medical, dental, and vision plans; flexible time off; family planning and parental leave; 401K and retirement plans.
- **Engineering culture**: Strong focus on cutting-edge semiconductor and AI infrastructure technology. High concentration of senior (24%) and specialist (19%) talent. Active internship and new graduate programs.
- **Employee ratings**: 4.5/5.0 on LinkedIn (124 reviews), with high marks for compensation (4.6), culture (4.4), and career development (4.4).

## Sources
1. [Astera Labs Careers Page](https://www.asteralabs.com/careers/)
2. [Astera Labs Official Website](https://www.asteralabs.com/)
3. [Astera Labs LinkedIn](https://www.linkedin.com/company/astera-labs)
4. [Astera Labs Products Page](https://www.asteralabs.com/products/)
5. [Astera Labs S-1 Filing (SEC)](https://ir.asteralabs.com/static-files/7103a4cb-aa6b-4f11-a4b0-f179cd4c5bee)

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