--- title: 'Sr. Staff PCB Design Engineer at d-Matrix' canonical: 'https://feeny.ai/job/sr-staff-pcb-design-engineer-d-matrix-santa-clara-hz690ae06epe' type: 'job' last_seen: '2026-09-11' --- # Sr. Staff PCB Design Engineer at d-Matrix - **Company:** d-Matrix - **Location:** Santa Clara, CA - **Compensation:** $175k–$265k - **Employment:** full-time - **Work type:** hybrid - **Posted:** 2026-08-28 - **Last confirmed live:** 2026-09-11 - **Apply:** https://jobs.ashbyhq.com/d-matrix/94b0f4c6-563c-4042-a4e8-ed6071213bbd ## Job description At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together, we can help shape the endless possibilities of AI. ## Role Overview As Sr. Staff PCB Design Engineer, you will lead the physical design of the boards that connect d-Matrix's AI silicon to the world. Our "Corsair" platforms push the limits of signal density and power delivery, and you will own layout for high-complexity, high-layer-count PCBAs (20+ layers) — ensuring 112G/224G SerDes signals stay clean and thousands of amps are delivered with minimal loss. Beyond hands-on layout, you will serve as custodian of our Design Methodology, driving the automation, tooling, and constraint management processes that let hardware development scale with precision and speed. You'll partner closely with power, ASIC, and manufacturing teams, and have the autonomy to build layout infrastructure from the ground up. ## What You Will Do - Lead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboards - Architect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraints - Develop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reporting - Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects - Partner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICs - Drive PCB stack-up definition, including advanced low-loss materials (e.g., Megtron 7/8) and hybrid build-ups - Serve as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production ## What You Will Bring - BS in Electrical/Electronic Engineering or equivalent practical experience - 10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators - Proficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching - Proven ability to write and deploy SKILL scripts or use Allegro's API to automate design audits and layout routines - Deep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC design - Proven track record routing 112G SerDes and complex DDR5/HBM interfaces ## Preferred Qualifications - Experience establishing a Library Management System and standardized footprint/padstack creation processes - Familiarity with PLM/PDM integration for managing layout releases and ECO workflows - Knowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMs ## Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation. ## About d-Matrix ## Company Overview - **One-liner**: d-Matrix is building ultra-low latency, memory-centric AI inference hardware and software platforms for datacenter-scale generative AI workloads. - **Entity Type**: Private (Series C, total raised ~$429M–$450M per conflicting reports) - **Headquarters**: Santa Clara, California, USA - **Founded**: 2019 - **Founders**: Sid Sheth (CEO) & Sudeep Bhoja (CTO / Founder) ## Core Business - **Primary industries**: AI infrastructure, semiconductor / hardware acceleration, datacenter compute - **Target customers**: Cloud providers, enterprises running large-scale generative AI inference (B2B) - **Mission / purpose**: To transform AI from unsustainable to attainable by breaking through limits of latency, cost, and energy in inference. ## Products & Services - **Corsair™** – AI inference accelerator platform (PCIe form factor, chiplet-based, 3D stacked DRAM) purpose-built for the decode phase of disaggregated inference. Works alongside GPUs for low-latency interactive AI. - **JetStream™** – Purpose-built I/O accelerator for AI inference (networking fabric to scale accelerator-to-accelerator communication). - **Aviator** – Software stack that orchestrates and optimizes inference workloads on d-Matrix hardware. - **SquadRack™** – Industry’s first rack-scale, disaggregated standards-based solution for AI inference, built with infrastructure partners. ## Market Standing - **Valuation**: Not publicly disclosed (private company) - **Key metric**: Total funding – $429M (per CB Insights) or $450M (per company blog after $275M Series C). Series C announced in late 2025 / early 2026. - **Notable investors**: Temasek, M12 (Microsoft’s venture arm), Playground Global, Nautilus Venture Partners, Industry Ventures, Mirae Asset Financial Group, Triatomic Capital, Bullhound Capital. - **Growth signals**: - Corsair entered full production in June 2026. - Won “AI Processor Innovation Award” from AI Breakthrough in June 2026. - Filed 21+ patents in parallel computing, neural networks, NLP. - Opened engineering offices in Santa Clara, Toronto, Bengaluru, Sydney, and Belgrade – global expansion underway. ## Competitive Advantages - **Memory-centric compute architecture (3DIMC™)** that eliminates latency bottlenecks caused by traditional memory-bound AI inference. - Chiplet-based design enables scaling to 100B+ parameter models in a PCIe form factor. - Disaggregated, standards-based rack-scale approach (SquadRack) that integrates seamlessly with existing datacenter infrastructure. - Team of industry veterans who have shipped over 100 million chips and generated $5B+ in prior revenue. ## Strategic Focus - Scaling production of Corsair to meet customer demand for agentic AI workloads (voice agents, coding tools, real-time inference). - Building a heterogeneous compute ecosystem where d-Matrix accelerators complement GPUs rather than replace them. - Expanding software stack (Aviator) and networking (JetStream) to deliver full-stack inference solutions. ## Why Work Here - **Culture**: “Round pegs in square holes” – builders, innovators, dreamers. Emphasis on humility, direct communication, and collaboration. - **Work model**: Remote & hybrid working model (global offices in Silicon Valley, Sydney, Bengaluru, Toronto, Belgrade). - **Benefits**: Competitive pay and equity, health care, flexible time-off, paid paternity leave, 401k, on-site fitness centers, free food/snacks, peer coaching & development, team-building activities. - **Engineering environment**: Work with world-leading engineers and researchers on cutting-edge AI hardware/software. Opportunity to shape the future of AI inference infrastructure. ## Sources 1. [d-matrix.ai – Homepage](https://www.d-matrix.ai/) 2. [d-matrix.ai – About / Leadership](https://www.d-matrix.ai/about/) 3. [d-matrix.ai – Careers](https://www.d-matrix.ai/careers/) 4. [d-matrix.ai – Corsair Production & AI Breakthrough Award](https://www.d-matrix.ai/announcements/d-matrix-corsair-ai-inference-platform-enters-full-production-to-meet-customer-demand/) 5. [CB Insights – d-Matrix Company Profile](https://www.cbinsights.com/company/d-matrix) 6. [Ashby – d-Matrix Jobs](https://jobs.ashbyhq.com/d-matrix) ## Other roles at d-Matrix - [HR Technology & Analytics Manager](https://feeny.ai/job/hr-technology-analytics-manager-d-matrix-santa-clara-k9cwmb1c8tnv) — Santa Clara, CA - [Principal, Printed Circuits Boards Manufacturing Engineer](https://feeny.ai/job/principal-printed-circuits-boards-manufacturing-engineer-d-matrix-santa-clara-5g46spc5gaea) — Santa Clara, CA - [Principal Architect, Performance Analysis and Modeling](https://feeny.ai/job/principal-architect-performance-analysis-and-modeling-d-matrix-santa-clara-ed109hz0sxd5) — Santa Clara, CA - [Staff Analog Design Engineer, TX/RX Datapath](https://feeny.ai/job/staff-analog-design-engineer-tx-rx-datapath-d-matrix-santa-clara-j59mraszxvs2) — Santa Clara, CA - [Staff Analog Design Engineer, SerDes Clocking](https://feeny.ai/job/staff-analog-design-engineer-serdes-clocking-d-matrix-santa-clara-jhh8m4s9cc3p) — Santa Clara, CA - [Senior Staff LLM Inference Engineer](https://feeny.ai/job/senior-staff-llm-inference-engineer-d-matrix-santa-clara-ee1s9qcfrvp6) — Santa Clara, CA - [Manufacturing Test Engineer, Staff](https://feeny.ai/job/manufacturing-test-engineer-staff-d-matrix-taipei-9ecpjbm8nm5g) — Taipei, Taiwan - [Senior Staff Operations Program Manager](https://feeny.ai/job/senior-staff-operations-program-manager-d-matrix-santa-clara-bm2psm0v0pz0) — Santa Clara, CA - [Staff Technical Recruiter - Contract](https://feeny.ai/job/staff-technical-recruiter-contract-d-matrix-bengaluru-b7qgjsg4kcz2) — Bengaluru, India - [Technical Program Manager - Hardware/Systems, Principal](https://feeny.ai/job/technical-program-manager-hardware-systems-principal-d-matrix-santa-clara-ce5k7tq47qwf) — Santa Clara, CA