---
title: 'Staff Analog Design Engineer, TX/RX Datapath at d-Matrix'
canonical: 'https://feeny.ai/job/staff-analog-design-engineer-tx-rx-datapath-d-matrix-santa-clara-j59mraszxvs2'
type: 'job'
last_seen: '2026-09-11'
---

# Staff Analog Design Engineer, TX/RX Datapath at d-Matrix

- **Company:** d-Matrix
- **Location:** Santa Clara, CA
- **Compensation:** $155k–$250k
- **Employment:** full-time
- **Work type:** hybrid
- **Posted:** 2026-08-19
- **Last confirmed live:** 2026-09-11
- **Apply:** https://jobs.ashbyhq.com/d-matrix/c3432cd7-f61b-4023-8e18-68d30c4aeee9

## Job description

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together, we can help shape the endless possibilities of AI.

## Role Overview

You will own the transmit and receive datapath of the high-speed SerDes on d-Matrix's IO chiplet — the interconnect that lets our inference accelerators scale beyond a single package. This is a hands-on, transistor-level design role on a small team, where you will personally carry blocks from specification through silicon characterization rather than handing specs off to someone else. The work spans porting proven datapath blocks to new process nodes and ground-up design of new blocks for our next-generation link, working closely with layout, package/signal-integrity, backend, and firmware engineers to bring your designs to working silicon.

## What You Will Do

- Own transistor-level design of the SerDes transmit path: output drivers (SST and/or CML), pre-driver and serializer stages, and transmit-side FFE.
- Own transistor-level design of the receive front-end: termination and ESD-aware input network, CTLE, VGA, samplers, and where applicable ADC-based front-ends.
- Design and verify the equalization path — DFE and FFE architecture, tap resolution, and adaptation behavior — and own the trade study behind the architecture you choose.
- Derive block-level specifications from link budgets covering insertion loss, crosstalk, reflection, jitter, and BER targets, and defend those specifications in design review.
- Build the verification environment for your blocks — testbenches, PVT corner coverage, six-sigma Monte Carlo, transient noise, and post-layout back-annotated simulation — and provide behavioral and Verilog-A models for full-chip verification, supporting backend engineers through integration.
- Perform link and channel modeling in MATLAB, Python, or equivalent — S-parameter channel and package models, statistical eye and BER analysis, and equalization trade studies.
- Drive layout of your blocks in deep sub-micron nodes, working with layout engineers on floorplan, matching, shielding, current density, and parasitic control, and co-designing with package/signal-integrity engineers on bump maps, escape routing, and channel budgets.
- Contribute to testboard design, then take your blocks through silicon bring-up and bench characterization, correlating measured performance against simulation.

## What You Will Bring

- BS/MS/PhD in Electrical Engineering, with 8+ years of hands-on analog and mixed-signal circuit design experience.
- Demonstrated ownership of a SerDes transmit or receive datapath block through to working silicon in a high-speed link.
- Deep knowledge of high-speed driver design, receive front-end design, and equalization, with practical familiarity with the adjacent clocking and CDR blocks your datapath interfaces with.
- Practical command of jitter and noise analysis — decomposition, budgeting, and the simulation methodology to quantify each contributor.
- Circuit design experience in advanced FinFET or GAA process nodes, with hands-on use of industry-standard analog design and simulation tools and methodologies (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation) and link/channel modeling (e.g., MATLAB, Python, S-parameter models).
- Silicon bring-up and bench debug experience with high-speed lab equipment such as scopes and BERTs, with the judgment to distinguish a design problem from a measurement problem.

## Preferred

- Die-to-die interconnect experience — UCIe, BoW, or a proprietary D2D PHY — including the specific constraints of short-reach, low-energy-per-bit links.
- PAM4 signaling and DSP-based receiver architectures, including ADC-based front-ends.
- Familiarity with relevant specifications: UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7.
- Experience porting a datapath block across process nodes, with a realistic sense of what that effort actually costs.
- IBIS-AMI model generation, or SerDes ATE and production test development.
- Participation in or contribution to standards bodies.

## Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

## About d-Matrix

## Company Overview
- **One-liner**: d-Matrix is building ultra-low latency, memory-centric AI inference hardware and software platforms for datacenter-scale generative AI workloads.
- **Entity Type**: Private (Series C, total raised ~$429M–$450M per conflicting reports)
- **Headquarters**: Santa Clara, California, USA
- **Founded**: 2019
- **Founders**: Sid Sheth (CEO) & Sudeep Bhoja (CTO / Founder)

## Core Business
- **Primary industries**: AI infrastructure, semiconductor / hardware acceleration, datacenter compute
- **Target customers**: Cloud providers, enterprises running large-scale generative AI inference (B2B)
- **Mission / purpose**: To transform AI from unsustainable to attainable by breaking through limits of latency, cost, and energy in inference.

## Products & Services
- **Corsair™** – AI inference accelerator platform (PCIe form factor, chiplet-based, 3D stacked DRAM) purpose-built for the decode phase of disaggregated inference. Works alongside GPUs for low-latency interactive AI.
- **JetStream™** – Purpose-built I/O accelerator for AI inference (networking fabric to scale accelerator-to-accelerator communication).
- **Aviator** – Software stack that orchestrates and optimizes inference workloads on d-Matrix hardware.
- **SquadRack™** – Industry’s first rack-scale, disaggregated standards-based solution for AI inference, built with infrastructure partners.

## Market Standing
- **Valuation**: Not publicly disclosed (private company)
- **Key metric**: Total funding – $429M (per CB Insights) or $450M (per company blog after $275M Series C). Series C announced in late 2025 / early 2026.
- **Notable investors**: Temasek, M12 (Microsoft’s venture arm), Playground Global, Nautilus Venture Partners, Industry Ventures, Mirae Asset Financial Group, Triatomic Capital, Bullhound Capital.
- **Growth signals**:
  - Corsair entered full production in June 2026.
  - Won “AI Processor Innovation Award” from AI Breakthrough in June 2026.
  - Filed 21+ patents in parallel computing, neural networks, NLP.
  - Opened engineering offices in Santa Clara, Toronto, Bengaluru, Sydney, and Belgrade – global expansion underway.

## Competitive Advantages
- **Memory-centric compute architecture (3DIMC™)** that eliminates latency bottlenecks caused by traditional memory-bound AI inference.
- Chiplet-based design enables scaling to 100B+ parameter models in a PCIe form factor.
- Disaggregated, standards-based rack-scale approach (SquadRack) that integrates seamlessly with existing datacenter infrastructure.
- Team of industry veterans who have shipped over 100 million chips and generated $5B+ in prior revenue.

## Strategic Focus
- Scaling production of Corsair to meet customer demand for agentic AI workloads (voice agents, coding tools, real-time inference).
- Building a heterogeneous compute ecosystem where d-Matrix accelerators complement GPUs rather than replace them.
- Expanding software stack (Aviator) and networking (JetStream) to deliver full-stack inference solutions.

## Why Work Here
- **Culture**: “Round pegs in square holes” – builders, innovators, dreamers. Emphasis on humility, direct communication, and collaboration.
- **Work model**: Remote & hybrid working model (global offices in Silicon Valley, Sydney, Bengaluru, Toronto, Belgrade).
- **Benefits**: Competitive pay and equity, health care, flexible time-off, paid paternity leave, 401k, on-site fitness centers, free food/snacks, peer coaching & development, team-building activities.
- **Engineering environment**: Work with world-leading engineers and researchers on cutting-edge AI hardware/software. Opportunity to shape the future of AI inference infrastructure.

## Sources
1. [d-matrix.ai – Homepage](https://www.d-matrix.ai/)
2. [d-matrix.ai – About / Leadership](https://www.d-matrix.ai/about/)
3. [d-matrix.ai – Careers](https://www.d-matrix.ai/careers/)
4. [d-matrix.ai – Corsair Production & AI Breakthrough Award](https://www.d-matrix.ai/announcements/d-matrix-corsair-ai-inference-platform-enters-full-production-to-meet-customer-demand/)
5. [CB Insights – d-Matrix Company Profile](https://www.cbinsights.com/company/d-matrix)
6. [Ashby – d-Matrix Jobs](https://jobs.ashbyhq.com/d-matrix)

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