---
title: 'Staff Engineer: STA Methodology & Sign-off Lead at EnCharge AI'
canonical: 'https://feeny.ai/job/staff-engineer-sta-methodology-sign-off-lead-encharge-ai-bengaluru-dnr9280vbw00'
type: 'job'
last_seen: '2026-09-12'
---

# Staff Engineer: STA Methodology & Sign-off Lead at EnCharge AI

- **Company:** EnCharge AI
- **Location:** Bengaluru, India
- **Posted:** 2026-07-23
- **Last confirmed live:** 2026-09-12
- **Apply:** https://job-boards.greenhouse.io/enchargeai36/jobs/4329845009

## Job description

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Staff Engineer: STA Methodology & Sign-off Lead

We are seeking a high-caliber Staff or Senior Staff Engineer to architect and lead our SOC Static Timing Analysis (STA) Methodology along with execution responsibilities to eliminate the bottle-necks in STA and build bridges.

This is a critical  role for a  forward-thinking engineer who excels at defining the frameworks and flows required to navigate the complexities of modern, large-scale SOC designs. Engineer will have scope to bridge Architecture, CAD, RTL, and Physical Design to establish a predictable, high-performance, and scalable path to tape-out.

The Role As the lead for STA Methodology, you will own the sign-off architecture and the timing convergence strategy. Rather than just executing runs, you will build the "engine" that enables execution—defining flows, qualifying tools, establishing margin strategies (AOCV/LVF/POCV), and driving cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets.

## Key Responsibilities

- Sign-off Methodology & Architecture: Define and own full-chip SOC timing sign-off criteria, including Multi-Mode Multi-Corner (MMMC) definitions, derate strategies, and operating condition mapping for functional, shift, and capture modes.
- Flow Development & Left-Shift Automation: Architect, deploy, and maintain advanced STA and ECO flows. Develop methodologies to proactively identify structural timing issues and predict physical design bottlenecks early in the RTL/Synthesis phases.
- Tool Benchmarking & Deployment: Evaluate, qualify, and deploy new EDA tool features and capabilities (with a strong emphasis on Cadence Tempus) to improve Quality of Results (QoR), optimize memory/runtime efficiency, and streamline hierarchical timing models.
- Custom Automation Infrastructure: Architect scalable, robust automation utilities (Tcl, Python, Perl) to standardize constraint (SDC) management, automate cross-domain timing audits, and accelerate the ECO loop across distributed design teams.
- Cross-Functional Enablement: Partner with Physical Design to define optimal clock tree synthesis (CTS) methodologies and floorplanning guidelines. Guide DFT and RTL teams on methodology to resolve structural bottlenecks (e.g., NoC timing, complex CDC paths).

## Requirements & Qualifications

- Experience: 8 to 11 years of hands-on experience in VLSI design, with a primary focus on STA Methodology, flow development, and sign-off criteria at advanced process nodes (7nm, 5nm, or below).
- Technical Mastery:
- Deep expertise in building flows around industry-standard sign-off tools, with a strong preference for Cadence Tempus.
- Mastery of Multi-Mode Multi-Corner (MMMC) flow architecture, Hierarchical (ILM/ETM) vs. Flat timing strategies, and constraint (SDC) validation methodologies.
- Strong understanding of advanced node timing phenomena, including waveform propagation, crosstalk, and statistical margining (LVF/POCV).
- Critical Thinking: Proven ability to architect broad flow solutions and debug systemic tool or methodology bottlenecks, rather than just fixing isolated timing violations.
- Soft Skills: Strong leadership presence with the ability to define technical standards, influence cross-functional teams, and drive methodology adoption in a fast-paced, high-growth environment.
- Education: B.Tech/M.Tech in Electrical/Electronics Engineering or a related field.

## About EnCharge AI

## Company Overview
- **One-liner**: EnCharge AI develops analog in-memory computing hardware and software to deliver high-efficiency, low-cost AI inference from edge devices to cloud data centers.
- **Entity Type**: Private (Series B – II stage)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2022
- **Founders**: Naveen Verma, Ph.D. (CEO) and Kailash Gopalakrishnan, Ph.D. (CTO)

## Core Business
- **Primary industry**: AI semiconductor hardware and embedded software products
- **Target customers**: B2B – enterprises deploying AI at scale, edge-device manufacturers, cloud service providers, and defense/industrial sectors
- **Mission**: Democratize advanced AI by enabling deployment beyond cloud infrastructure to local servers and mobile devices, while slashing costs and environmental impact

## Products & Services
- **Analog In-Memory Computing GPUs & Digital AI Accelerators**: Custom silicon (chiplets, ASICs) and standard-form-factor PCIe cards that perform AI inference using analog computation for orders-of-magnitude better energy efficiency and compute density.
- **Software Stack**: Seamless orchestration layer that supports on-device and cloud deployment, enabling model portability, quantization, and compiler optimizations across EnCharge’s hardware.
- **Edge-to-Cloud Platforms**: Integrated solutions for power-, space-, and cost-constrained environments, covering autonomous systems, smart devices, data center inference, and private on-premise AI.

## Market Standing
- **Valuation / Market Cap**: Not publicly disclosed
- **Key Metrics**: Annual Revenue ~$10M (LinkedIn estimate) | Total Funding $162.9M
- **Notable Investors & Partners**: Tiger Global Management (led $100M Series B, Mar 2025), Anzu Partners (led $21.7M Series A, Dec 2022), DARPA ($18.6M grant, Mar 2024), and others including corporate/institutional backers.
- **Growth Signals**: 
  - 58.6% YoY headcount growth (75 employees, as of mid-2025)
  - 39 active job openings spanning hardware, compiler, and AI architecture roles
  - 150+ patents granted, 300+ technical publications
  - Talent inflows from Intel, IBM, Cerebras, AMD, Meta, Microsoft

## Competitive Advantages
- **Analog In-Memory Computing Moa**t: A proprietary compute architecture that uses charge-domain analog circuits, validated silicon, and leverages existing semiconductor supply chains.
- **Record Efficiency**: Claims 20× higher TOPS/W, 9× higher compute density (TOPS/mm²), 10× lower total cost of ownership, and 100× lower CO₂ emissions compared to leading cloud/GPU alternatives.
- **Deep IP Portfolio**: 150+ granted patents and 300+ publications from 20+ years of foundational research by the founding team (Princeton, IBM, etc.).
- **End-to-End Solution**: Full-stack hardware and software (compiler, quantization, runtime) designed for seamless edge-to-cloud orchestration without vendor lock-in.

## Strategic Focus
- Scale production and customer deployments of their analog in-memory compute chips for high-volume edge and data center inference.
- Expand software ecosystem to support mainstream AI frameworks (PyTorch, TensorFlow, ONNX) and enable easy drop-in replacement for existing GPU-accelerated workloads.
- Deepen partnerships with defense (DARPA) and enterprise cloud providers, emphasizing data privacy, security, and sustainability.
- Double down on sustainability messaging (100× lower CO₂) to meet ESG mandates in enterprise AI procurement.

## Why Work Here
- **Mission-Driven Impact**: Opportunity to make AI accessible to the “99%” by dramatically reducing energy and cost barriers. Work is cited as a “once-in-a-lifetime” chance by leadership.
- **World-Class Team**: Colleagues include industry luminaries from Princeton, IBM, and top semiconductor houses; 57% of staff are in technical roles (engineering, research, compiler).
- **Culture of Collaboration & Innovation**: The careers page highlights integrity, growth, and collaborative problem-solving in a fast-paced startup environment.
- **Comprehensive Rewards**: Benefits package includes typical startup perks; equity likely offered given funding stage.
- **Work Policy**: Hybrid presence indicated by offices in Santa Clara, Canada, Germany, Norway, South Korea, and India. Remote flexibility likely for some roles.
- **Active Hiring**: 39 open positions across DFT, physical design, compiler engineering, and NPU architecture – strong signal of scaling and technical investment.

## Sources
1. [EnCharge AI Official Website](https://www.enchargeai.com/)
2. [EnCharge AI Careers Page](https://www.enchargeai.com/careers)
3. [EnCharge AI About Us (Leadership & Founders)](https://www.enchargeai.com/about-us)
4. [EnCharge AI LinkedIn Company Page](https://www.linkedin.com/company/encharge-ai)
5. [CB Insights Profile – EnCharge AI](https://www.cbinsights.com/company/encharge-ai)

## Other roles at EnCharge AI

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- [Principal Solutions Engineer](https://feeny.ai/job/principal-solutions-engineer-encharge-ai-united-states-vgghgxj68g9h) — United States
- [Lead DFT Engineer](https://feeny.ai/job/lead-dft-engineer-encharge-ai-canada-united-states-q4ggksnf4q7g) — Canada / United States
- [Senior PD Engineer: Synthesis & STA](https://feeny.ai/job/senior-pd-engineer-synthesis-sta-encharge-ai-bengaluru-wfbtaq6984et) — Bengaluru, India
- [Senior Staff / Principal SOC Floorplan Lead](https://feeny.ai/job/senior-staff-principal-soc-floorplan-lead-encharge-ai-bengaluru-5rjzbdmx1e0r) — Bengaluru, India
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