--- title: 'Staff / Senior Staff CAD & Methodology Engineer (Digital Implementation & Signoff) at EnCharge AI' canonical: 'https://feeny.ai/job/staff-senior-staff-cad-methodology-engineer-digital-implementation-signoff-bbfjk21sk0rk' type: 'job' last_seen: '2026-09-05' --- # Staff / Senior Staff CAD & Methodology Engineer (Digital Implementation & Signoff) at EnCharge AI - **Company:** EnCharge AI - **Location:** Bengaluru, India - **Work type:** hybrid - **Posted:** 2026-07-10 - **Last confirmed live:** 2026-09-05 - **Apply:** https://job-boards.greenhouse.io/enchargeai36/jobs/4312902009 ## Job description EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. We are an ambitious AI hardware startup building next-generation accelerators with massive compute density. To achieve aggressive Power, Performance, and Area (PPA) targets on accelerated tapeout schedules, we require a robust, highly automated, and heavily optimized physical implementation and signoff flow. ## The Role As a Staff / Senior Staff CAD & Methodology Engineer, you will be the resident expert in Innovus and Tempus, responsible for developing, debugging, and continually accelerating our RTL-to-GDSII and timing signoff flows. You will work closely with Physical Design and STA leads to eliminate bottlenecks, automate manual tasks, and push the limits of EDA capabilities at advanced process nodes. ## Key Responsibilities - Flow Architecture & Automation: Architect, develop, and maintain a highly automated, robust, and scalable physical design and signoff flow from synthesis through GDSII, optimized for AI accelerator architectures. - Innovus Methodology: Drive advanced physical design methodologies in Cadence Innovus. Optimize recipes for floorplanning, placement, Clock Tree Synthesis (CTS), routing, and power grid implementation to squeeze out maximum PPA. - Tempus Signoff Integration: Own the STA and timing signoff methodology using Cadence Tempus. Implement and optimize Distributed Multi-Scenario Analysis (DMSA), advanced OCV methodologies, and automated Tempus ECO flows to ensure rapid timing closure. - Turnaround Time (TAT) Reduction: Identify inefficiencies in the daily execution of block and top-level implementation. Develop Python and Tcl-based automation, database parsers, and custom utilities to drastically reduce tool runtime and engineering debug time. - Tool & Vendor Interface: Act as the primary technical liaison with Cadence. Drive tool evaluations, beta testing of new features, and resolution of critical tool bugs or limitations to ensure continuous flow stability. - Mentorship & Support: Serve as the final escalation point for the PD and Timing teams regarding flow-related issues. Document methodologies clearly and mentor junior engineers on tool usage and flow mechanics. ## Requirements & Qualifications - Experience: 9 to 14 years of industry experience in ASIC/SOC physical design, with a primary focus on CAD, TFM (Tools, Flows, and Methodology), or flow automation. - Cadence Mastery: - - Deep, production-proven expertise with Cadence Innovus (Implementation) and Cadence Tempus (Signoff STA). - - Strong understanding of internal tool mechanics, database access commands (dbGet), and advanced tool configuration. - Scripting & Software Skills: Expert-level proficiency in Tcl and Python. Strong background in Makefile generation, shell scripting, and version control (Git/Perforce). - Domain Knowledge: Thorough understanding of deep sub-micron physical design concepts (advanced node DRCs, cross-talk, electromigration, IR drop) and the theoretical foundations of Static Timing Analysis. - Startup Mindset: Ability to thrive in a fast-paced, dynamic environment where flow requirements evolve rapidly as the architecture matures. - Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline. ## About EnCharge AI ## Company Overview - **One-liner**: EnCharge AI develops analog in-memory computing hardware and software to deliver high-efficiency, low-cost AI inference from edge devices to cloud data centers. - **Entity Type**: Private (Series B – II stage) - **Headquarters**: Santa Clara, California, United States - **Founded**: 2022 - **Founders**: Naveen Verma, Ph.D. (CEO) and Kailash Gopalakrishnan, Ph.D. (CTO) ## Core Business - **Primary industry**: AI semiconductor hardware and embedded software products - **Target customers**: B2B – enterprises deploying AI at scale, edge-device manufacturers, cloud service providers, and defense/industrial sectors - **Mission**: Democratize advanced AI by enabling deployment beyond cloud infrastructure to local servers and mobile devices, while slashing costs and environmental impact ## Products & Services - **Analog In-Memory Computing GPUs & Digital AI Accelerators**: Custom silicon (chiplets, ASICs) and standard-form-factor PCIe cards that perform AI inference using analog computation for orders-of-magnitude better energy efficiency and compute density. - **Software Stack**: Seamless orchestration layer that supports on-device and cloud deployment, enabling model portability, quantization, and compiler optimizations across EnCharge’s hardware. - **Edge-to-Cloud Platforms**: Integrated solutions for power-, space-, and cost-constrained environments, covering autonomous systems, smart devices, data center inference, and private on-premise AI. ## Market Standing - **Valuation / Market Cap**: Not publicly disclosed - **Key Metrics**: Annual Revenue ~$10M (LinkedIn estimate) | Total Funding $162.9M - **Notable Investors & Partners**: Tiger Global Management (led $100M Series B, Mar 2025), Anzu Partners (led $21.7M Series A, Dec 2022), DARPA ($18.6M grant, Mar 2024), and others including corporate/institutional backers. - **Growth Signals**: - 58.6% YoY headcount growth (75 employees, as of mid-2025) - 39 active job openings spanning hardware, compiler, and AI architecture roles - 150+ patents granted, 300+ technical publications - Talent inflows from Intel, IBM, Cerebras, AMD, Meta, Microsoft ## Competitive Advantages - **Analog In-Memory Computing Moa**t: A proprietary compute architecture that uses charge-domain analog circuits, validated silicon, and leverages existing semiconductor supply chains. - **Record Efficiency**: Claims 20× higher TOPS/W, 9× higher compute density (TOPS/mm²), 10× lower total cost of ownership, and 100× lower CO₂ emissions compared to leading cloud/GPU alternatives. - **Deep IP Portfolio**: 150+ granted patents and 300+ publications from 20+ years of foundational research by the founding team (Princeton, IBM, etc.). - **End-to-End Solution**: Full-stack hardware and software (compiler, quantization, runtime) designed for seamless edge-to-cloud orchestration without vendor lock-in. ## Strategic Focus - Scale production and customer deployments of their analog in-memory compute chips for high-volume edge and data center inference. - Expand software ecosystem to support mainstream AI frameworks (PyTorch, TensorFlow, ONNX) and enable easy drop-in replacement for existing GPU-accelerated workloads. - Deepen partnerships with defense (DARPA) and enterprise cloud providers, emphasizing data privacy, security, and sustainability. - Double down on sustainability messaging (100× lower CO₂) to meet ESG mandates in enterprise AI procurement. ## Why Work Here - **Mission-Driven Impact**: Opportunity to make AI accessible to the “99%” by dramatically reducing energy and cost barriers. Work is cited as a “once-in-a-lifetime” chance by leadership. - **World-Class Team**: Colleagues include industry luminaries from Princeton, IBM, and top semiconductor houses; 57% of staff are in technical roles (engineering, research, compiler). - **Culture of Collaboration & Innovation**: The careers page highlights integrity, growth, and collaborative problem-solving in a fast-paced startup environment. - **Comprehensive Rewards**: Benefits package includes typical startup perks; equity likely offered given funding stage. - **Work Policy**: Hybrid presence indicated by offices in Santa Clara, Canada, Germany, Norway, South Korea, and India. Remote flexibility likely for some roles. - **Active Hiring**: 39 open positions across DFT, physical design, compiler engineering, and NPU architecture – strong signal of scaling and technical investment. ## Sources 1. [EnCharge AI Official Website](https://www.enchargeai.com/) 2. [EnCharge AI Careers Page](https://www.enchargeai.com/careers) 3. [EnCharge AI About Us (Leadership & Founders)](https://www.enchargeai.com/about-us) 4. [EnCharge AI LinkedIn Company Page](https://www.linkedin.com/company/encharge-ai) 5. [CB Insights Profile – EnCharge AI](https://www.cbinsights.com/company/encharge-ai) ## Other roles at EnCharge AI - [Technical Program Manager - Embedded Software](https://feeny.ai/job/technical-program-manager-embedded-software-encharge-ai-united-states-w18v49ve3s0r) — United States - [Principal Solutions Engineer](https://feeny.ai/job/principal-solutions-engineer-encharge-ai-united-states-vgghgxj68g9h) — United States - [Lead DFT Engineer](https://feeny.ai/job/lead-dft-engineer-encharge-ai-canada-united-states-q4ggksnf4q7g) — Canada / United States - [Senior PD Engineer: Synthesis & STA](https://feeny.ai/job/senior-pd-engineer-synthesis-sta-encharge-ai-bengaluru-wfbtaq6984et) — Bengaluru, India - [Senior Staff / Principal SOC Floorplan Lead](https://feeny.ai/job/senior-staff-principal-soc-floorplan-lead-encharge-ai-bengaluru-5rjzbdmx1e0r) — Bengaluru, India - [Staff Engineer: STA Methodology & Sign-off Lead](https://feeny.ai/job/staff-engineer-sta-methodology-sign-off-lead-encharge-ai-bengaluru-dnr9280vbw00) — Bengaluru, India - [Principal SOC Physical Verification & Integration Specialist](https://feeny.ai/job/principal-soc-physical-verification-integration-specialist-encharge-ai-bengaluru-z28meksf9r5v) — Bengaluru, India - [Research Engineer, AI Models](https://feeny.ai/job/research-engineer-ai-models-encharge-ai-germany-5kv1pnxdmybd) — Germany - [Research Engineer, AI Models](https://feeny.ai/job/research-engineer-ai-models-encharge-ai-india-s35hk7vzfyr3) — India - [AI Compiler Engineer](https://feeny.ai/job/ai-compiler-engineer-encharge-ai-united-states-canada-germany-norway-qxpwrahb89wk) — United States / Canada / Germany / Norway