--- title: 'Staff Systems Engineer, Calibration, Bring-Up & Verification at Neurophos' canonical: 'https://feeny.ai/job/staff-systems-engineer-calibration-bring-up-verification-neurophos-austin-zdned888ahts' type: 'job' last_seen: '2026-10-19' --- # Staff Systems Engineer, Calibration, Bring-Up & Verification at Neurophos - **Company:** Neurophos - **Location:** Austin, TX - **Compensation:** $185k–$215k - **Employment:** full-time - **Work type:** onsite - **Posted:** 2026-09-18 - **Last confirmed live:** 2026-10-19 - **Apply:** https://jobs.ashbyhq.com/neurophos/f286e763-fa39-4b01-a449-f0c3d231d078 ## Job description ## About Neurophos The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach. Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference. We’ve assembled a world-class team of industry veterans and recently raised a [$110M Series A](https://www.neurophos.com/110m-raise) led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. Join us and shape the future of computing! Location: Austin, TX. Full-time onsite position. Reports To: Chief Systems Engineer FLSA Status: Exempt Position Overview We are seeking a highly skilled Systems Engineer to own calibration architecture, system integration, and verification for our optical vector-matrix multiplication (OVMM) engine. This role is central to closing the gap between a system that is designed to meet its accuracy targets and one that demonstrably does so on the bench: you will devise the calibration algorithms that correct optical phase, amplitude, and timing across many channels, specify the analog and digital hardware structures needed for real-time calibration execution, define the bring-up and verification strategy, and personally drive laboratory characterization of the hardware. You will spend much of your time devising calibration algorithms grounded in control theory and signal processing, and the rest of it hands-on in the lab, bringing up hardware, running verification plans, characterizing performance, and tracking down exactly where measured behavior departs from the model. If you combine control-theory and signal-processing depth with genuine enthusiasm for lab work, this role will let you own the path from calibrated silicon to a working, verified system. ## Key Responsibilities Primary Responsibilities - Calibration Architecture: Define the calibration architecture for the OVMM system, and scope and size the algorithms needed to correct optical phase, amplitude, and timing across many transmit and receive channels. - Calibration Algorithm Development: Design, implement, and optimize calibration algorithms, applying control theory and optimization techniques to minimize calibration time while meeting system accuracy targets. - Signal Processing for Calibration: Design and implement signal processing techniques used within calibration loops to enhance measurement SNR through coding gain and noise bandwidth reduction. - Calibration Data Compression: Develop techniques and algorithms to compress calibration data and minimize on-chip and off-chip storage requirements. - HW/SW/Control Interaction: Specify the calibration controller behavior, apply paths, and digital hardware structures needed to execute calibration in silicon, and define the calibration software and firmware interfaces that drive them. - System Integration Strategy & Bring-Up: Define the system integration strategy, plan the integration sequence, and lead laboratory bring-up and debug of the assembled system, establishing acceptance criteria at each subassembly boundary. - Observability & Diagnostics: Define system-level test, diagnostic, and observability requirements so that bring-up, calibration, and field operation can all distinguish a healthy system from a degraded one. - Verification & Characterization: Develop verification plans, execute performance characterization in the lab, and correlate measured results with modeled predictions, identifying and root-causing gaps between the two. Secondary Responsibilities - Develop calibration control and test software (primarily Python) used both in the lab during bring-up and as the basis for production calibration flows. - Supply the Signal-Path Performance & Modeling team with calibration accuracy budgets and sensitivity data derived from lab measurements. - Flag to the Architecture & Requirements team any interface or requirement that impedes calibration, bring-up, or verification. - Mentor engineers in calibration algorithm design, bring-up practice, and laboratory characterization methodology. ## Qualifications - Degree: MS or PhD in Electrical Engineering, Applied Physics, or a closely related field, with emphasis on control systems, signal processing, or mixed-signal systems. - Experience: 5+ years of professional experience in calibration algorithm development, system bring-up, or verification of complex electro-optic or mixed-signal systems. - Control & Optimization Theory: Strong foundation in feedback control (stability analysis, sampled-data systems) and optimization methods (convex optimization, gradient descent, search algorithms), with demonstrated ability to formulate a calibration problem as a formal optimization problem and solve it efficiently. - Analog System Understanding: Deep understanding of analog and mixed-signal impairments including noise (thermal, shot, flicker), component mismatches, nonlinearities (compression, harmonic distortion), bandwidth limitations, and their impact on system-level performance metrics (SNR, BER, ENOB). Ability to theoretically predict calibration performance from first principles. - Digital Hardware Awareness: Good understanding of digital hardware design principles, including logic synthesis, area and power estimation, state machine design, and fixed-point arithmetic, sufficient to specify calibration hardware that is implementable within realistic silicon constraints. Familiarity with RTL design concepts and hardware-software partitioning. - Lab & Verification: Hands-on experience bringing up and debugging complex hardware using oscilloscopes, spectrum/network analyzers, and optical test equipment, and correlating measured performance against a model. - Software for Calibration: Proficiency developing calibration and test software (Python and/or MATLAB), including control loops, data acquisition, and automated characterization scripts, sufficient to run and iterate on lab measurements independently. - Communication: Excellent communication skills for cross-functional collaboration with analog IC designers, digital designers, photonic device engineers, and system architects. ## Preferred Skills - Practical experience with digital signal processing techniques, including spectral analysis, correlation, and adaptive filtering, applied within calibration or measurement loops. - Familiarity with Cadence Virtuoso and Spectre for validating calibration-relevant behavioral models against circuit-level simulation. - Exposure to Bayesian optimization, machine learning for system calibration, or statistical design of experiments. - Experience with optical transceiver calibration, phased-array beamforming, or ADC/DAC calibration. ## What We Offer This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world. ## Benefits Join a team that invests in your future and your well-being. At Neurophos, we offer: - 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions. - Unlimited PTO. No rigid vacation banks, just a focus on delivery. - 401(k) matching and stock option opportunities to ensure our success is your success. - Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance. - Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t. ## About Neurophos ## Company Overview - **One-liner**: Neurophos develops photonic AI chips (Optical Processing Units) that perform matrix multiplications at the speed of light, aiming to replace traditional GPUs in data-center inference workloads. - **Entity Type**: Private, Series A - **Headquarters**: Austin, Texas, USA (with an additional office in San Jose, California) - **Founded**: 2020 - **Founders**: Patrick Bowen (CEO, Co-Founder) and Andrew Traverso (Chief Scientist, Co-Founder); other co-founders may include Preston Woo and Hod Finkelstein (CEO, CTO roles indicated on team page). ## Core Business - **Primary industry**: Semiconductor / Photonic AI Hardware - **Target customers**: B2B – hyperscale data centers, enterprise AI infrastructure providers - **Mission/purpose**: “We’re building the first programmable light-speed computer” – solving energy and scalability challenges in AI data centers by using optical rather than electronic computation. ## Products & Services - **Optical Processing Unit (OPU)**: A photonic AI chip that integrates over one million micron-scale optical processing components on a single die. It performs matrix multiplications in-memory at the speed of light, delivering up to 100x the energy efficiency of traditional GPUs and NVIDIA servers while fitting in a single-GPU form factor. The chip uses an active, programmable metasurface and silicon photonics to achieve 0.47 ExaOPS performance in a 1m x 1m footprint. First systems are targeted for early 2028, with production ramp in mid-2028. ## Market Standing - **Valuation/Market Cap**: Not disclosed - **Key Metric**: Total funding raised = **$119.2M** (including a $110M Series A closed in early 2026) - **Notable Investors**: Gates Frontier (lead), M12 (Microsoft’s venture fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, MetaVC Partners, Gaingels, Mana Ventures, and 22+ others. - **Growth Signals**: - Recognized on EE Times Silicon 100 list for several consecutive years. - Over 300 patents filed and protected. - Rapid hiring after Series A – “hypergrowth phase” as per press release. - Team includes veterans from NVIDIA, AMD, Apple, Meta, Google, Magic Leap, Micron, Qualcomm, Samsung, and other photonic/AR companies. ## Competitive Advantages - **Metasurface optical transistors** that are **10,000x smaller** than traditional photonic components, enabling unprecedented density – millions of weights fit in the area of a postage stamp. - **300+ patents** covering optical metamaterials, neural network accelerators, and machine learning hardware. - **Energy efficiency**: Up to 100x improvement over existing electronic solutions (e.g., GPUs), directly addressing the power constraints of hyperscale AI inference. - **Size/performance**: OPU delivers the performance of a 3,000-pound server in the size and power envelope of a single GPU. ## Strategic Focus - **Commercialization**: First customer evaluations begin in 2026; first OPU systems target early 2028 production ramp. - **Talent acquisition**: Scaling the team aggressively across analog design, photonics, architecture, and software to meet “hypergrowth” demand. - **Partnerships**: Leveraging investors like Bosch Ventures (industrial IoT), Aramco Ventures (energy), and M12 (cloud/AI) to align with large-scale data center customers. ## Why Work Here - **Culture**: In-office, on‑site work culture in Austin, TX (primary) and San Jose, CA. Described as a “world-class team” with leaders from top semiconductor and tech companies. - **Growth**: Joining at a hypergrowth scale‑up stage with significant funding and a clear path to production; opportunities to shape the architecture and engineering of a new computing paradigm. - **Engineering focus**: 34 out of 40 total employees are in product + tech roles, indicating a highly technical, R&D-driven environment. - **Impact**: Work on cutting-edge optical computing that could redefine AI hardware efficiency; involvement in everything from silicon photonics to compiler software. - **Notable perks**: Not explicitly listed, but being a well-funded deep-tech startup likely offers competitive equity, technical challenges, and direct mentorship from industry veterans. ## Sources 1. [neurophos.com](https://www.neurophos.com/) 2. [neurophos.com/careers](https://www.neurophos.com/careers) 3. [neurophos.com/team](https://www.neurophos.com/team) 4. [cbinsights.com](https://www.cbinsights.com/company/neurophos) 5. [builtin.com](https://builtin.com/company/neurophos) ## Other roles at Neurophos - [Principal Systems Engineer, Signal-Path Performance & Modeling](https://feeny.ai/job/principal-systems-engineer-signal-path-performance-modeling-neurophos-austin-tk4yrtdgtw9z) — Austin, TX - [Senior/Staff BEOL Process Integration Engineer](https://feeny.ai/job/senior-staff-beol-process-integration-engineer-neurophos-leuven-t70g32b8rjvj) — Leuven, Belgium - [Chief Engineer, Prototype System Integration and Experimentation](https://feeny.ai/job/chief-engineer-prototype-system-integration-and-experimentation-neurophos-austin-25tqc715f1xs) — Austin, TX - [Director of Analog and Mixed-Signal IC Design](https://feeny.ai/job/director-of-analog-and-mixed-signal-ic-design-neurophos-austin-3p5774p64xsn) — Austin, TX - [Senior Manager, People Operations](https://feeny.ai/job/senior-manager-people-operations-neurophos-austin-hyephpnwweqx) — Austin, TX - [Senior Recruiting Coordinator](https://feeny.ai/job/senior-recruiting-coordinator-neurophos-austin-ca7canrrcvk8) — Austin, TX - [Design for Test Lead](https://feeny.ai/job/design-for-test-lead-neurophos-austin-x7waft3dx2ky) — Austin, TX - [Staff Systems Engineer, Signal-Path Performance & Modeling](https://feeny.ai/job/staff-systems-engineer-signal-path-performance-modeling-neurophos-austin-hgj4br5t99pp) — Austin, TX - [Design Verification Lead](https://feeny.ai/job/design-verification-lead-neurophos-austin-9pcn9jqa3gzx) — Austin, TX - [Staff Technical Program Manager, ASIC](https://feeny.ai/job/staff-technical-program-manager-asic-neurophos-austin-mhx7d9bs15a4) — Austin, TX