---
title: 'Synthesis & Static Timing Analysis (STA) Engineer at Voltai'
canonical: 'https://feeny.ai/job/synthesis-static-timing-analysis-sta-engineer-voltai-palo-alto-2a8m8rdmwxqw'
type: 'job'
last_seen: '2026-11-03'
---

# Synthesis & Static Timing Analysis (STA) Engineer at Voltai

- **Company:** Voltai
- **Location:** Palo Alto, CA
- **Employment:** full-time
- **Posted:** 2026-10-19
- **Last confirmed live:** 2026-11-03
- **Apply:** https://jobs.ashbyhq.com/voltai.careers/7c63cbec-6567-4e75-a953-a6f1668ff70b

## Job description

## About Voltai

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.

## About the Team

Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.

## About this Role

You'll own the path from RTL to a timing-clean netlist. You'll close timing on real silicon programs with leading semiconductor companies while helping Voltai's AI learn to write constraints, diagnose violations, and close timing.

## What You’ll Do

- Own logic synthesis and constraint development (SDC) for blocks and full chips.
- Drive timing closure across corners and modes, working with RTL and physical design teams.
- Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis.
- Perform logic equivalence checking between RTL and netlist.
- Build automation that makes synthesis and timing flows faster and more reliable.
- Evaluate AI-generated constraints and timing fixes, and help define what good looks like.

## What We’re Looking For

- 5+ years of synthesis and STA experience on production tapeouts.
- Deep experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus.
- Strong SDC skills: clocks, exceptions, generated clocks, and multi-mode constraints.
- Experience with logic equivalence checking (Formality or Conformal).
- Strong Tcl and Python scripting.

Bonus Points

- Advanced node experience (7nm and below).
- Experience with ECO flows and timing signoff methodology.
- Interest in AI-assisted design tools.

## About Voltai

## Company Overview
- **One-liner**: Voltai develops AI models and agentic systems that learn, plan, and experiment to design PCBs, ASICs, and other semiconductor/electronics hardware, aiming to surpass human cognitive limits in physical-world engineering.
- **Entity Type**: Private (Seed-stage – pre-seed funding round reported in October 2025)
- **Headquarters**: Palo Alto, United States (also has presence in Germany)
- **Founded**: 2015 (as per Tracxn; recent operational activity suggests a more current iteration)
- **Founders**: Not publicly named as co-founders; current CEO is Priyanka Mathikshara (per Tracxn), CSO is Labib Tazwar Rahman (per LinkedIn). The team includes former Stanford professors, SAIL researchers, and alumni from Synopsys, GlobalFoundries, and Cadence.

## Core Business
- **Primary industry**: AI for semiconductor and electronics design (hardware design automation)
- **Target customers**: B2B – the world’s largest semiconductor companies, consumer electronics makers, automotive OEMs, and sovereign nations
- **Mission or purpose statement**: To build superintelligent systems that can reason across the entire hardware-software-manufacturing stack, enabling the next frontier of physical-world engineering.

## Products & Services
- **[Voltai AI Platform]**: A suite of AI models and agents that co-design electronics and semiconductors. The system uses world models to run billions of virtual experiments, bypassing the prohibitive cost and time of physical prototyping. Outputs include PCB layouts, ASIC designs, and manufacturing blueprints. (Type: AI/ML SaaS with physical verification)

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Raised CAD$1.83M in pre-seed funding in October 2025 from Invest Nova Scotia, Cloudberry Pioneer Investments, and others (conflicting with Tracxn’s “unfunded” status – see Sources).
- **Notable Investors/Partners**: Backed by “Silicon Valley’s top investors”, Stanford University, and executives/CEOs of Google, AMD, and Broadcom (per website). Strategic partners include major semiconductor and consumer electronics firms.
- **Growth Signals**: Headcount grew ~600% YoY (from very small base); currently 3–4 employees with 27 active job postings (as of mid-2026). Website claims partnerships with “most of the world’s largest semiconductor companies” and sovereign nations.

## Competitive Advantages
- **Domain-specific foundation models**: Unlike general-purpose AI, Voltai’s models are trained on proprietary real-world hardware data and can reason over long horizons (months-to-years design cycles).
- **World model simulation**: Runs billions of experiments in silico, a unique capability that reduces the need for costly physical tape-outs.
- **Elite talent pool**: Team includes former CTOs of Synopsys and GlobalFoundries, a former US Secretary of Defense, and Olympic medalists (IPhO, IOI) – an unusually deep combination of AI research and semiconductor executive experience.
- **Board-level strategic priority**: Already has commitments from top-tier semiconductor and consumer electronics companies, including sovereign nations, giving it rare access and validation.

## Strategic Focus
- **Current priorities**: Scaling the AI platform to cover the full electronics stack (from PCB to ASIC to manufacturing); hiring aggressively across research (post-training, CUDA kernel engineering), hardware engineering (system, power, server), and enterprise sales; expanding partnerships with global semiconductor leaders.

## Why Work Here
- **Culture**: Emphasizes high-agency, interdisciplinary work at the intersection of AI and physical engineering. The team includes Olympiad medalists and former CTOs – a “smartest in the room” environment.
- **Remote/hybrid policy**: Fully remote (as indicated on Built In and LinkedIn). Employees work from the United States and Germany.
- **Notable perks**: Opportunity to work on frontier AI problems with direct impact on the semiconductor industry; access to unrivaled industry partners and compute resources.
- **Engineering culture**: Heavy focus on research engineering (CUDA, post-training, systems), with open roles for both software and hardware engineers. Emphasis on real-world validation and iterative experimentation.

## Sources
1. [voltai.com](https://www.voltai.com/)
2. [LinkedIn – Voltai](https://www.linkedin.com/company/voltai-inc)
3. [Built In – Voltai Careers](https://builtin.com/company/voltai)
4. [Tracxn – Voltai Company Profile](https://tracxn.com/d/companies/voltai/__HV-xuXnVpXmBMrSANdeEmHzMlZPWefz9YZpOVAklfDE)
5. [FinSMEs – Voltai Raises CAD$1.83M in Pre-Seed Funding](https://www.finsmes.com) (referenced in search snippet)
6. [Ashby – Voltai Careers Page](https://jobs.ashbyhq.com/voltai.careers)

## Other roles at Voltai

- [Post-Silicon Validation Engineer](https://feeny.ai/job/post-silicon-validation-engineer-voltai-palo-alto-30at1qgx90ee) — Palo Alto, CA
- [Design for Test (DFT) Engineer](https://feeny.ai/job/design-for-test-dft-engineer-voltai-palo-alto-5tq4746e1185) — Palo Alto, CA
- [CAD & Flow Methodology Engineer](https://feeny.ai/job/cad-flow-methodology-engineer-voltai-palo-alto-cmcdwkan4j3c) — Palo Alto, CA
- [Physical Verification & Signoff Engineer](https://feeny.ai/job/physical-verification-signoff-engineer-voltai-palo-alto-vzr2kj3x8nm1) — Palo Alto, CA
- [Emulation & FPGA Prototyping Engineer](https://feeny.ai/job/emulation-fpga-prototyping-engineer-voltai-palo-alto-zd9w554vr1j3) — Palo Alto, CA
- [Low-Power Design Engineer](https://feeny.ai/job/low-power-design-engineer-voltai-palo-alto-tm5ra7jy855y) — Palo Alto, CA
- [Physical Design Engineer](https://feeny.ai/job/physical-design-engineer-voltai-palo-alto-dv8nzq3tm7p4) — Palo Alto, CA
- [RTL Design Engineer](https://feeny.ai/job/rtl-design-engineer-voltai-palo-alto-6w6stk6md5hw) — Palo Alto, CA
- [Chip Architect](https://feeny.ai/job/chip-architect-voltai-palo-alto-fd3hd3ssn1bw) — Palo Alto, CA
- [Forward Deployed Engineer](https://feeny.ai/job/forward-deployed-engineer-voltai-palo-alto-w0zz0fy01p0a) — Palo Alto, CA