---
title: 'Systems Validation Engineer, L10 at Etched'
canonical: 'https://feeny.ai/job/systems-validation-engineer-l10-etched-san-jose-7mh66dfe67fq'
type: 'job'
last_seen: '2026-09-07'
---

# Systems Validation Engineer, L10 at Etched

- **Company:** [Etched](https://feeny.ai/companies/etched)
- **Location:** San Jose, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-04-27
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.ashbyhq.com/etched/78bca8a9-69e9-4066-a14c-ae562bf98520/application

**Skills:** System validation, Platform bring-up, Signal integrity debug, Power integrity debug, SerDes, PCIe Gen5/6, Ethernet, HBM signaling, Linux, Python, Bash, AI accelerator validation, High-performance compute platforms, BMC/IPMI, UEFI/BIOS bring-up, CPLD firmware debug, HBM validation, CSRAM memory subsystem validation, Multi-rack system validation, Llama-class inference workloads

> The L10 System Validation Engineer defines production-ready standards for the accelerator platform, building infrastructure to prove readiness and driving critical issues from detection to resolution. This role involves end-to-end debug of hardware failures, managing system bring-up across accelerator cards and inte...

## Job description

## About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

You will be the L10 System Validation Engineer, defining what it means for the accelerator platform to be production-ready. You'll be responsible for building our Cluster Scale Memory subsystem and build the infrastructure to prove it. You'll personally drive the most critical issues from detection through root cause to verified fix.

## Key Responsibilities

- Author and own the L10 system debug guide, serving as the definitive reference for factory failure analysis and debug teams.
- Own end-to-end escalation, debug, and resolution of L10 hardware failures across internal and field teams
- Develop and own L10 system debug guide to be used for the factory by the failure analysis / debug team.
- Own bring-up and integration across accelerator cards, interconnects (Retimers, C2C fabric), power (PSU, power integrity), and thermal domains.
- Lead system-level debug with no guaranteed starting point: hardware, firmware (BMC, BIOS, CPLD), and software all in scope simultaneously.
- Partner directly with CMs to validate incomplete systems, close coverage gaps, and gate production ramp.
- Build ad-hoc instrumentation, automation scripts, and debug workflows to extract signals from unstable, pre-spec systems.
- Run sustained workloads using real model variants under thermal and power stress
- Drive issue closure across cross-functional engineering teams: HW, FW, SW, thermal, power, and manufacturing.
- Represent validation readiness to leadership with crisp, data-backed assessments

You may be a good fit if you have (Must-have qualifications)

- 10+ years in system validation, platform bring-up, or a tightly adjacent discipline — with direct, solo ownership of full L10 (tray/rack) integration on multi-component platforms.
- Demonstrated hands-on signal integrity and power integrity debug: SerDes, PCIe Gen5/6, Ethernet, HBM signaling
- Proven ability to build a coverage model that produces quantitative platform readiness metrics
- Strong Linux and Python/Bash scripting — you should be comfortable writing tools to instrument, automate, and extract data from systems that aren't fully debuggable yet.
- Occasional travel overseas to contract manufactures
- Experience validating AI accelerator or high-performance compute platforms with accelerators, NVMe, high-speed interconnects, and complex power delivery.
- Track record of detecting integration issues before they escape to production — in environments where specs, tooling, and infrastructure were still being built.

Strong candidates may also have experience with (Nice-to-have qualifications)

- Familiarity with BMC/IPMI, UEFI/BIOS bring-up, and CPLD firmware debug.
- Experience with HBM or CSRAM memory subsystem validation.
- Background validating multi-rack or tray-level systems at hyperscaler or AI hardware company scale.
- Exposure to large-model inference workloads as stress and coverage tools.
- Prior work with ODM/CM partners (Pegatron, Foxconn, Wistron, or equivalent) in a validation or NPI capacity.

What success looks like

- Critical escapes to production are zero — not because nothing broke, but because you assumed everything would break and proved otherwise.
- You created a structure where there was none: coverage models, automation, debug workflows, and RCA templates exist because you built them.
- Platform stress runs are stable, repeatable, and instrument-verified under sustained thermal and power load.
- Manufacturing partners have clear, data-driven pass/fail gates — and they trust the gates because you defined them.
- Engineering leadership has a real-time, quantified view of platform readiness at every stage of ramp.

## Benefits

- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in our office
- Unlimited compute budget subject to ROI justification

## How we’re different

Etched believes in the Bitter Lesson http://www.incompleteideas.net/IncIdeas/BitterLesson.html. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

## About Etched

## Company Overview
- **One-liner**: Etched designs and manufactures specialized ASICs (application-specific integrated circuits) that are hardwired to run transformer-based AI models, offering an order-of-magnitude improvement in inference cost and energy efficiency over general-purpose GPUs.
- **Entity Type**: Private (Series B / later stage; total raised $800M as of June 2026)
- **Headquarters**: San Jose, California, USA (also has offices in Cupertino, CA; Sacramento, CA; and small presence in Taiwan, Canada, UK, Bulgaria)
- **Founded**: 2022
- **Founders**: Gavin Uberti (CEO), Robert Wachen (President & COO), Chris Zhu (Co-Founder)

## Core Business
- **Primary industry**: AI hardware / semiconductor design / computer hardware manufacturing
- **Target customers**: Frontier AI labs, hyperscalers, and enterprises running large-scale transformer inference workloads (B2B, enterprise)
- **Mission / purpose**: Build hardware for superintelligence – specifically, the world’s most powerful servers for transformer inference.

## Products & Services
- **Sohu Chip (ASIC)**: A transformer-specific ASIC manufactured by TSMC. It burns the transformer architecture directly into silicon, eliminating the overhead of general-purpose GPUs for inference.
- **Frontier Inference Clusters**: Full-stack systems that bundle the Sohu chip with custom-designed racks, networking, and software. Customers place orders for complete systems, not just chips. Etched claims they deliver more tokens per dollar and per watt for dense models, sparse MoEs, diffusion models, and more.
- **Software Stack**: Includes compiler and runtime optimizations built by a team with deep experience (former Apache TVM developer, ex-Google TPU software lead).

## Market Standing
- **Valuation**: $5 billion post-money valuation (as of December 2025 / disclosed June 2026)
- **Key Metric**: $1 billion in contract orders (booked) for its systems; total funding of $800M (including an unannounced $500M round closed Dec 2025 led by Stripes)
- **Notable Investors**: Stripes (lead), VentureTech Alliance, Jane Street, Hudson River Trading, Two Sigma, Ribbit Capital. Angel investors include Andrej Karpathy, Geoffrey Hinton, Fei-Fei Li, Arthur Mensch, Scott Wu, Stanley Druckenmiller, Peter Thiel. Earlier backers: Positive Sum, Primary Venture Partners.
- **Growth Signals**:
  - Headcount: 258 employees (as of mid-2026), up 141% year-over-year
  - 100+ active job postings across engineering, operations, and business functions
  - $500M raise in late 2025; first chip manufactured by TSMC in 2025 and now being tested with customers
  - Talent sources include Google (21), Apple (17), NVIDIA (16), Tesla (11), Intel (10), AMD (5)

## Competitive Advantages
- **Transformer-specific architecture**: Unlike GPUs (which are general-purpose), Etched’s chip is hardwired only for transformer operations, enabling drastically lower cost and latency for today’s dominant AI model architecture.
- **Full-stack system play**: By selling entire inference clusters (chip + rack + software), Etched captures more value and delivers a turnkey solution competitive with NVIDIA’s DGX/HGX systems.
- **Deeply experienced leadership**:
  - CEO Gavin Uberti (Harvard math researcher, AI compiler expert, Apache TVM contributor)
  - President Robert Wachen (co-founded Prod AI incubator; Thiel Fellow)
  - VP of Platform (ex-NVIDIA 22 years, built HGX/DGX systems)
  - VP of Software (ex-Google DeepMind, lead TPU v1–v5 software)
  - Chief Architect Saptadeep Pal (former Auradine co-founder, chiplet expert)
  - VP of Hardware Engineering Ajat Hukkoo (ex-Cypress CTO, shipped >$1B revenue products)

## Strategic Focus
- **Scale manufacturing and customer deliveries**: With the first chip successfully fabricated, the company is now testing production systems and aims to fulfill $1B in pre-orders.
- **Expand engineering talent**: Aggressively hiring across silicon design, validation, infrastructure, optics, and software to support volume ramp.
- **Maintain technological lead**: Continue refining the ASIC for future transformer variants and MoE mixtures while building out a partner ecosystem.

## Why Work Here
- **Mission-driven, high-impact engineering**: “Building the hardware for superintelligence” – the company is solving one of the hardest problems in compute (inference efficiency) with a focused team.
- **Top-tier team and learning environment**: Colleagues from Google, NVIDIA, Apple, Tesla, Broadcom, and Intel; exposure to full-stack chip-to-system design.
- **In-office culture**: All roles are in-office (Cupertino and San Jose, CA). The company emphasizes on-site collaboration for hardware development. Notable perks are not heavily advertised, but compensation is competitive for the AI hardware space (equity-heavy).
- **Growth trajectory**: 141% headcount growth YoY, hundreds of open roles, and a $5B valuation signal strong backing and career acceleration potential.
- **Intellectual challenge**: Work on chip simulation, RTL design, system validation, or software infrastructure for cutting-edge AI inference.

## Sources
1. [etched.com/careers](https://www.etched.com/careers)
2. [builtin.com/company/etched](https://builtin.com/company/etched)
3. [linkedin.com/company/etched-ai](https://www.linkedin.com/company/etched-ai)
4. [cbinsights.com/company/etched](https://www.cbinsights.com/company/etched)
5. [techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/](https://techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/)

## Other roles at Etched

- [EE Hardware System Engineer (TW)](https://feeny.ai/job/ee-hardware-system-engineer-tw-etched-taipei-fgncym9kzy6w) — Taipei, Taiwan
- [Silicon Validation Engineer, Software](https://feeny.ai/job/silicon-validation-engineer-software-etched-san-jose-qhp3k9xqy5vr) — San Jose, CA
- [RMA & Repair Lead](https://feeny.ai/job/rma-repair-lead-etched-san-jose-q0tmchh0yyrj) — San Jose, CA
- [Advanced Packaging SI/PI Engineer](https://feeny.ai/job/advanced-packaging-si-pi-engineer-etched-san-jose-47he7k0hp901) — San Jose, CA
- [Substrate IC Package Layout Design Engineer](https://feeny.ai/job/substrate-ic-package-layout-design-engineer-etched-san-jose-g36wmxc8ww9r) — San Jose, CA
- [ECAD Librarian](https://feeny.ai/job/ecad-librarian-etched-san-jose-0h5kvj2cxzk4) — San Jose, CA
- [Inventory Warehouse Coordinator](https://feeny.ai/job/inventory-warehouse-coordinator-etched-san-jose-49b0bs49ce57) — San Jose, CA
- [Logistics Analyst (Taiwan)](https://feeny.ai/job/logistics-analyst-taiwan-etched-taipei-5xzc094cqgzn) — Taipei, Taiwan
- [Communications](https://feeny.ai/job/communications-etched-san-jose-3f4bdr97hysp) — San Jose, CA
- [Production Finance](https://feeny.ai/job/production-finance-etched-san-jose-qfypbv9eh0ws) — San Jose, CA