---
title: 'Tech Lead– Verification Methodology/CAD at Astera Labs'
canonical: 'https://feeny.ai/job/tech-lead-verification-methodology-cad-astera-labs-bengaluru-f5wq84qsng9e'
type: 'job'
last_seen: '2026-11-06'
---

# Tech Lead– Verification Methodology/CAD at Astera Labs

- **Company:** Astera Labs
- **Location:** Bengaluru, India
- **Posted:** 2026-08-27
- **Last confirmed live:** 2026-11-06
- **Apply:** https://job-boards.greenhouse.io/asteralabs/jobs/4728420005

## Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/).

TechLead– Verification Methodology / CAD / Automation Engineer

## Experience - 6–12 years

Job Summary

We are looking for a Tech Lead – Verification Methodology/CAD/Automation Engineer to drive verification infrastructure, methodology, automation, and productivity across IP and SoC verification teams.

The candidate will build scalable verification frameworks, automate verification workflows, improve regression infrastructure, and partner with design verification teams to establish efficient and reusable methodologies.

## Key Responsibilities

- Own and drive verification methodology and infrastructure across projects.
- Develop scalable frameworks for simulation, regression, coverage, debug, and verification signoff.
- Build and maintain verification CAD/automation flows.
- Develop automation scripts and tools using Python, Tcl, Perl, Shell, and/or C++.
- Automate test generation, compilation, regression execution, result collection, coverage analysis, and reporting.
- Develop infrastructure for large-scale UVM/SystemVerilog verification environments.
- Improve simulation and regression turnaround time through parallelization and optimization.
- Integrate simulation, lint, CDC/RDC, formal, coverage, and other verification tools into common workflows.
- Develop dashboards and metrics for verification quality, coverage, regression health, and project status.
- Debug infrastructure and tool-flow issues and provide rapid support to verification teams.
- Establish reusable verification components, scripts, libraries, and methodology guidelines.
- Drive adoption of best practices across multiple verification teams.
- Evaluate new verification technologies and tools and recommend improvements.
- Work closely with EDA vendors to troubleshoot tool issues and improve flows.
- Support migration and integration of new EDA tool versions and methodologies.
- Develop documentation and training for verification teams.
- Mentor verification CAD/methodology engineers and provide technical leadership.

Required Technical Skills

- Strong experience in verification methodology, CAD, and automation.
- Strong programming/scripting skills in Python, Tcl, Perl, Shell, and preferably C/C++.
- Strong understanding of SystemVerilog/UVM.
- Experience with simulation tools such as VCS, Xcelium, Questa, or equivalent.
- Experience building and maintaining regression infrastructure.
- Strong knowledge of coverage collection and analysis.
- Understanding of verification flows including:
- Simulation
- UVM
- Lint
- CDC/RDC
- Formal
- Code/functional coverage
- Regression
- Debug
- Strong Linux/Unix environment experience.
- Excellent automation and problem-solving skills.

## Preferred Experience

- Experience with large-scale SoC/IP verification environments.
- Experience integrating multiple EDA tools into a unified verification flow.
- Experience with CI/CD infrastructure such as Jenkins, GitLab CI, or equivalent.
- Experience with distributed/parallel regression infrastructure.
- Experience with cloud-based or scalable compute environments.
- Knowledge of databases, dashboards, APIs, or web-based verification infrastructure is an advantage.
- Experience working with EDA vendors and managing tool-flow issues.

Leadership Expectations

- Act as the technical owner for verification methodology and automation.
- Identify opportunities to improve verification productivity, quality, and turnaround time.
- Define and enforce verification methodology standards.
- Mentor engineers and drive adoption of common frameworks.
- Work across multiple projects and teams to solve infrastructure challenges.
- Strong ability to balance immediate project requirements with long-term methodology improvements.

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Science, Computer Engineering, VLSI, or a related discipline.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## About Astera Labs

## Company Overview
- **One-liner**: Astera Labs designs and delivers semiconductor-based connectivity solutions purpose-built to unleash the full potential of cloud and AI infrastructure.
- **Entity Type**: Public (Nasdaq: ALAB)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2017
- **Founders**: Jitendra Mohan, Sanjay Gajendra, Casey Morrison

## Core Business
- **Primary industry**: Semiconductor manufacturing / AI infrastructure connectivity
- **Target customers**: B2B, primarily hyperscale cloud providers and system OEMs (e.g., NVIDIA, AMD, Intel)
- **Mission statement**: To innovate, design, and deliver semiconductor-based connectivity solutions that are purpose-built to unleash the full potential of cloud and AI infrastructure.

## Products & Services
- **Aries PCIe®/CXL™ Smart DSP Retimers**: Silicon ICs, boards, and modules that digitally recover degraded high-speed signals to extend reach and enable higher PCIe/CXL data bandwidth between compute, storage, and network controllers.
- **Taurus Ethernet Smart Cable Modules™**: Hardware modules that increase network connectivity bandwidth between servers and switches over copper media, removing rack-level Ethernet bottlenecks.
- **Leo CXL Memory Connectivity Controllers**: ICs and boards that expand, share, and pool DRAM memory to overcome processor memory bandwidth bottlenecks for AI workloads.
- **Scorpio Smart Fabric Switches**: A family of PCIe 6 fabric switches ranging from 32 to 320 lanes, including the new 320-lane Scorpio X-Series Fabric Switch for AI scale-up fabrics.
- **COSMOS Software Suite**: A connectivity system management and optimization software that enables configuration, monitoring, troubleshooting, and predictive analytics for all Astera Labs products.

## Market Standing
- **Market Cap**: ~$11.6 billion (as of mid-2026)
- **Key Metric - Revenue**: $35 million (annual, reported)
- **Key Metric - Operating Income**: $173.4 million (2025)
- **Key Metric - Net Income**: $219.1 million (2025)
- **Total Funding**: ~$810.75 million (pre-IPO), with Series C ($50M, led by Fidelity) and Series D ($150M, led by Fidelity)
- **IPO Date**: March 20, 2024
- **Notable Investors/Partners**: Fidelity, NVIDIA, Advanced Micro Devices, Intel, major hyperscalers
- **Growth Signals**: 92% YoY headcount growth (675 employees); 144 active job postings (+260% YoY); expanded Taiwan operations with a new Cloud-Scale Interop Lab in 2026; shipping millions of devices across all major hyperscalers; 300+ design wins.

## Competitive Advantages
- **First-to-market innovation**: Pioneered first-to-market PCIe, Ethernet, and CXL connectivity products.
- **Patented software-defined platform approach**: Differentiates via a platform that combines silicon hardware with embedded COSMOS software, enabling flexibility, observability, and predictive analytics.
- **Deep hyperscaler relationships**: Trusted partner to the world’s largest cloud providers, with proven interoperability validated in their own Cloud-Scale Interop Lab.
- **Broad product portfolio**: Covers PCIe retimers, Ethernet cable modules, CXL memory controllers, and fabric switches—addressing the full spectrum of AI connectivity bottlenecks.
- **Strong IP and engineering talent**: 443 employees in technical roles; talent sourced from Intel (65), Marvell (37), Texas Instruments (40), AMD (22), and NVIDIA.

## Strategic Focus
- **Scaling AI infrastructure**: Expanding product portfolio and global footprint (12 countries) to meet surging demand for rack-scale AI.
- **Open standards leadership**: All products are grounded in open standards (PCIe, CXL, Ethernet), ensuring interoperability and broad adoption.
- **Taiwan expansion**: Growing engineering presence and Interop Lab in Taiwan to strengthen integration with leading AI platform providers and system manufacturers.
- **Continued innovation**: Shipping the new 320-lane Scorpio X-Series Fabric Switch and expanding the COSMOS software suite for fleet-level management and optimization.

## Why Work Here
- **Culture**: Described as collaborative, ownership-driven, and focused on solving complex problems together. The company emphasizes diversity and inclusion as drivers of creativity and innovation.
- **Growth**: Astera Labs supports non-linear career growth—employees can deepen expertise (“scale up”) or broaden into new areas (“scale out”). 92% YoY headcount growth signals rapid expansion and opportunity.
- **Remote/Hybrid**: Not explicitly stated, but global operations across 12 countries (including India, Canada, Israel, Taiwan, Vietnam) suggest a flexible, distributed work model.
- **Benefits**: Competitive medical, dental, and vision plans; flexible time off; family planning and parental leave; 401K and retirement plans.
- **Engineering culture**: Strong focus on cutting-edge semiconductor and AI infrastructure technology. High concentration of senior (24%) and specialist (19%) talent. Active internship and new graduate programs.
- **Employee ratings**: 4.5/5.0 on LinkedIn (124 reviews), with high marks for compensation (4.6), culture (4.4), and career development (4.4).

## Sources
1. [Astera Labs Careers Page](https://www.asteralabs.com/careers/)
2. [Astera Labs Official Website](https://www.asteralabs.com/)
3. [Astera Labs LinkedIn](https://www.linkedin.com/company/astera-labs)
4. [Astera Labs Products Page](https://www.asteralabs.com/products/)
5. [Astera Labs S-1 Filing (SEC)](https://ir.asteralabs.com/static-files/7103a4cb-aa6b-4f11-a4b0-f179cd4c5bee)

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