---
title: 'Technical Lead Digital Design Engineer at Astera Labs'
canonical: 'https://feeny.ai/job/technical-lead-digital-design-engineer-astera-labs-san-jose-bdctbn8w3d2p'
type: 'job'
last_seen: '2026-11-06'
---

# Technical Lead Digital Design Engineer at Astera Labs

- **Company:** Astera Labs
- **Location:** San Jose, CA
- **Posted:** 2026-11-02
- **Last confirmed live:** 2026-11-06
- **Apply:** https://job-boards.greenhouse.io/asteralabs/jobs/4748103005

## Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/).

## Overview

Join our team as Technical Lead Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.

## Key Responsibilities

- Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
- Collaborate with verification teams to review test plans and debug issues.
- Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.
- Scripting and automation for ASIC methodology improvement.
- Accountable for quality and overall design success with the support of senior engineers.

Required Qualifications Education & Experience:

- Bachelor’s degree in electrical engineering or equivalent
- 5+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

- Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.
- Track record of delivering high-quality digital designs from definition to production.
- Experience in high-speed design in advanced technology nodes.
- Understanding of functional and formal verification at block and chip level.
- Understanding of clocking, CDC and RDC and static-timing analysis

Protocols & Integration:

- Proficient with high-speed protocols such as PCIe, Ethernet, DDR, or similar
- Experience with IP development and integration

Tools & Methodologies:

- Expertise in design methodology, CAD automation or design infrastructure.
- Proven SystemVerilog and Python expertise in a production environment
- Familiarity with Synopsys and/or Cadence digital design flows
- Basic understanding of UVM-based verification methodologies

Professional Attributes:

- Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment
- Good communication and collaboration skills; comfortable working cross-functionally with global teams
- Self-directed learner who adapts quickly to changing requirements
- Customer-focused mindset with the ability to prioritize and work independently to deliver high-quality designs.

## Preferred Qualifications

- Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus
- Knowledge of design-for-test (DFT) in a production environment.

Base salary range is $160,000 USD-$200,000 USD,and will be determined based on the candidate's capabilities and employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## About Astera Labs

## Company Overview
- **One-liner**: Astera Labs designs and delivers semiconductor-based connectivity solutions purpose-built to unleash the full potential of cloud and AI infrastructure.
- **Entity Type**: Public (Nasdaq: ALAB)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2017
- **Founders**: Jitendra Mohan, Sanjay Gajendra, Casey Morrison

## Core Business
- **Primary industry**: Semiconductor manufacturing / AI infrastructure connectivity
- **Target customers**: B2B, primarily hyperscale cloud providers and system OEMs (e.g., NVIDIA, AMD, Intel)
- **Mission statement**: To innovate, design, and deliver semiconductor-based connectivity solutions that are purpose-built to unleash the full potential of cloud and AI infrastructure.

## Products & Services
- **Aries PCIe®/CXL™ Smart DSP Retimers**: Silicon ICs, boards, and modules that digitally recover degraded high-speed signals to extend reach and enable higher PCIe/CXL data bandwidth between compute, storage, and network controllers.
- **Taurus Ethernet Smart Cable Modules™**: Hardware modules that increase network connectivity bandwidth between servers and switches over copper media, removing rack-level Ethernet bottlenecks.
- **Leo CXL Memory Connectivity Controllers**: ICs and boards that expand, share, and pool DRAM memory to overcome processor memory bandwidth bottlenecks for AI workloads.
- **Scorpio Smart Fabric Switches**: A family of PCIe 6 fabric switches ranging from 32 to 320 lanes, including the new 320-lane Scorpio X-Series Fabric Switch for AI scale-up fabrics.
- **COSMOS Software Suite**: A connectivity system management and optimization software that enables configuration, monitoring, troubleshooting, and predictive analytics for all Astera Labs products.

## Market Standing
- **Market Cap**: ~$11.6 billion (as of mid-2026)
- **Key Metric - Revenue**: $35 million (annual, reported)
- **Key Metric - Operating Income**: $173.4 million (2025)
- **Key Metric - Net Income**: $219.1 million (2025)
- **Total Funding**: ~$810.75 million (pre-IPO), with Series C ($50M, led by Fidelity) and Series D ($150M, led by Fidelity)
- **IPO Date**: March 20, 2024
- **Notable Investors/Partners**: Fidelity, NVIDIA, Advanced Micro Devices, Intel, major hyperscalers
- **Growth Signals**: 92% YoY headcount growth (675 employees); 144 active job postings (+260% YoY); expanded Taiwan operations with a new Cloud-Scale Interop Lab in 2026; shipping millions of devices across all major hyperscalers; 300+ design wins.

## Competitive Advantages
- **First-to-market innovation**: Pioneered first-to-market PCIe, Ethernet, and CXL connectivity products.
- **Patented software-defined platform approach**: Differentiates via a platform that combines silicon hardware with embedded COSMOS software, enabling flexibility, observability, and predictive analytics.
- **Deep hyperscaler relationships**: Trusted partner to the world’s largest cloud providers, with proven interoperability validated in their own Cloud-Scale Interop Lab.
- **Broad product portfolio**: Covers PCIe retimers, Ethernet cable modules, CXL memory controllers, and fabric switches—addressing the full spectrum of AI connectivity bottlenecks.
- **Strong IP and engineering talent**: 443 employees in technical roles; talent sourced from Intel (65), Marvell (37), Texas Instruments (40), AMD (22), and NVIDIA.

## Strategic Focus
- **Scaling AI infrastructure**: Expanding product portfolio and global footprint (12 countries) to meet surging demand for rack-scale AI.
- **Open standards leadership**: All products are grounded in open standards (PCIe, CXL, Ethernet), ensuring interoperability and broad adoption.
- **Taiwan expansion**: Growing engineering presence and Interop Lab in Taiwan to strengthen integration with leading AI platform providers and system manufacturers.
- **Continued innovation**: Shipping the new 320-lane Scorpio X-Series Fabric Switch and expanding the COSMOS software suite for fleet-level management and optimization.

## Why Work Here
- **Culture**: Described as collaborative, ownership-driven, and focused on solving complex problems together. The company emphasizes diversity and inclusion as drivers of creativity and innovation.
- **Growth**: Astera Labs supports non-linear career growth—employees can deepen expertise (“scale up”) or broaden into new areas (“scale out”). 92% YoY headcount growth signals rapid expansion and opportunity.
- **Remote/Hybrid**: Not explicitly stated, but global operations across 12 countries (including India, Canada, Israel, Taiwan, Vietnam) suggest a flexible, distributed work model.
- **Benefits**: Competitive medical, dental, and vision plans; flexible time off; family planning and parental leave; 401K and retirement plans.
- **Engineering culture**: Strong focus on cutting-edge semiconductor and AI infrastructure technology. High concentration of senior (24%) and specialist (19%) talent. Active internship and new graduate programs.
- **Employee ratings**: 4.5/5.0 on LinkedIn (124 reviews), with high marks for compensation (4.6), culture (4.4), and career development (4.4).

## Sources
1. [Astera Labs Careers Page](https://www.asteralabs.com/careers/)
2. [Astera Labs Official Website](https://www.asteralabs.com/)
3. [Astera Labs LinkedIn](https://www.linkedin.com/company/astera-labs)
4. [Astera Labs Products Page](https://www.asteralabs.com/products/)
5. [Astera Labs S-1 Filing (SEC)](https://ir.asteralabs.com/static-files/7103a4cb-aa6b-4f11-a4b0-f179cd4c5bee)

## Other roles at Astera Labs

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- [Lead Verification Engineer](https://feeny.ai/job/lead-verification-engineer-astera-labs-san-jose-qewac3xfs1m8) — San Jose, CA
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- [Staff/ Principal Physical Design STA Engineer](https://feeny.ai/job/staff-principal-physical-design-sta-engineer-astera-labs-haifa-district-zw1kz1hbapmp) — Haifa District, Israel