---
title: 'Technical Program Manager at Powerlattice Technologies Inc.'
canonical: 'https://feeny.ai/job/technical-program-manager-powerlattice-technologies-inc-hq-vancouver-canada-gc6h651g9nrf'
type: 'job'
last_seen: '2026-09-07'
---

# Technical Program Manager at Powerlattice Technologies Inc.

- **Company:** Powerlattice Technologies Inc.
- **Location:** HQ / Vancouver, Canada
- **Employment:** full-time
- **Work type:** hybrid
- **Posted:** 2026-08-21
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.ashbyhq.com/powerlattice/5471f329-445e-4198-9c19-9745d17eaef9

## Job description

Technical Program Manager

Reports To: CEO

Company Overview

Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.

## About the Role

We are seeking an experienced Technical Program Manager to drive execution of complex silicon IC and hardware development programs from concept through production. This role will partner closely with engineering, operations, supply chain, and external vendors to ensure successful delivery of high-quality products on aggressive schedules.

## Key Responsibilities

- Management of end-to-end engineering programs for silicon IC and hardware development projects from planning through production release.
- Drive cross-functional execution across ASIC/SoC design, verification, physical design, firmware, hardware, validation, operations, and manufacturing teams.
- Develop and maintain program schedules, milestones, dependencies, resource plans, and risk assessments.
- Coordinate closely with third-party vendors, design partners, contractors, and manufacturing suppliers to ensure deliverables meet schedule, quality, and cost targets.
- Track critical path items and proactively identify and resolve program risks, bottlenecks, and execution gaps.
- Drive alignment between engineering teams and external partners on priorities, schedules, deliverables, and issue resolution.
- Perform regular program reviews, status meetings, and executive updates.
- Manage silicon development milestones including specification freeze, RTL release, tape-out, package development, board bring-up, validation, and production readiness.
- Coordinate hardware development activities including PCB design, prototype builds, lab validation, and system integration.
- Support engineering change management, issue tracking, and escalation management processes.
- Ensure effective communication and coordination across geographically distributed teams and external vendors.
- Drive continuous improvement in program management processes, execution methodologies, and operational efficiency.

## Qualifications

This is a Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area). While we are primarily seeking candidates in HQ-Vancouver, remote flexibility may be considered for exceptional candidates in Chandler, AZ.

- Bachelor’s degree in Engineering, Computer Science, or related technical field.
- 8+ years of program management experience in semiconductor, ASIC/SoC, or hardware product development environments.
- Strong understanding of silicon IC development flows including architecture, design, verification, physical design, tapeout, bring-up, and production.
- Experience managing hardware development programs including PCB/system development and validation activities.
- Proven experience coordinating and driving execution with third-party vendors, design houses, manufacturing partners, and suppliers.
- Strong project planning and schedule management skills with the ability to manage complex cross-functional dependencies.
- Experience managing aggressive development schedules and multiple concurrent deliverables.
- Strong risk management, problem-solving, and decision-making skills.
- Excellent communication, leadership, and stakeholder management abilities.

Experience using program management and collaboration tools such as Jira, Confluence, Smartsheet, MS Project, or equivalent.

## Preferred Qualifications

- Experience managing mixed-signal SoC or high-performance silicon development programs.
- Familiarity with semiconductor manufacturing, packaging, test, and supply chain operations.
- Experience supporting silicon bring-up, validation, and production ramp activities.

## Compensation & Benefits

Anticipated annual base salary for Member of Technical Staff: $130,000 - $150,000

- Stock option grant
- Comprehensive benefits package including health, dental, vision, and 401(k)

## About Powerlattice Technologies Inc.

## Company Overview
- **One-liner**: PowerLattice reimagines power delivery for next-generation AI accelerators with the industry’s first power delivery chiplet, integrating voltage regulation directly into the processor package to break the AI power wall.
- **Entity Type**: Private (raised $25M in funding; stage not publicly specified)
- **Headquarters**: United States (specific city not publicly disclosed; offices in two US locations)
- **Founded**: Year not publicly available
- **Founders**: Dr. Peng Zou, Gang Ren, Sujith Dermal

## Core Business
- Primary industry: Semiconductor power delivery for AI accelerators, GPUs, and data-center processors
- Target customers: B2B – data center operators, AI hardware manufacturers, SoC designers
- Mission: “Reimagining power delivery for next-generation AI accelerators” by tightly integrating power and compute to achieve breakthrough performance, efficiency, and scalability.

## Products & Services
- **[Power Delivery Chiplet (Rainier micro-IVR architecture)]**: A monolithic chiplet that combines miniaturized on-die magnetic inductors, advanced control circuits, and a programmable software layer. It delivers voltage regulation directly inside the processor package, enabling 2-3X performance per watt, >50% reduction in power loss, and significantly extended system lifetime. Hardware product (chiplet) with software configurability.

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Total funding of $25M (announced on company website)
- **Notable Investors/Partners**: Investors include Steve Fu; board of directors includes Pat Gelsinger (former Intel CEO). Additional partners/backers not publicly detailed.
- **Growth Signals**: Early-stage company with a small team (10–20 employees per conflicting reports from BuiltIn); first-of-its-kind product targeting the urgent “power wall” problem in AI data centers; founders bring deep experience from Qualcomm, NUVIA, Intel, Huawei, and other top semiconductor firms.

## Competitive Advantages
- **On-die magnetic inductors** – miniaturized proprietary inductors integrated at the chip level, enabling tight coupling between power and compute.
- **Chiplet architecture** – scalable, configurable, and adaptable to any SoC power topology; can be embedded in substrates or interposers.
- **Order-of-magnitude reduction in power noise** and >50% reduction in effective compute power needs.
- **Performance uplift** – under fixed data center power budgets, translates into 2X or more raw performance uplift.
- **Founding team’s deep domain expertise** in power management, IVR, and high-volume IC design for tier-one customers (Apple, Samsung, Amazon).

## Strategic Focus
- Current priority: Productizing the power delivery chiplet and achieving design wins with major AI accelerator and GPU customers.
- Long-term direction: Scaling the chiplet architecture for next-generation data-center processors and expanding into broader high-performance computing markets.
- Focus on breaking the “power wall” that limits AI compute density and data center efficiency.

## Why Work Here
- **Culture**: Small, focused team working on hard problems at the intersection of hardware and innovation. Emphasizes curiosity, hands-on work, and real-world impact.
- **Work environment**: Remote-first with hybrid options; two US offices available. BuiltIn lists roles as “Remote Workspace” and “Hybrid”.
- **Perks**: Equity (stock options) offered. The company values thoughtful engineering and believes better power delivery can unlock new computing possibilities.
- **Engineering culture**: Deep technical challenges in analog/mixed-signal IC design, magnetic materials, system integration, and software. Opportunities to work with industry veterans and shape a groundbreaking product from early stage.

## Sources
1. [powerlatticeinc.com](https://powerlatticeinc.com/)
2. [powerlatticeinc.com/about](https://powerlatticeinc.com/about)
3. [powerlatticeinc.com/careers](https://powerlatticeinc.com/careers)
4. [builtin.com](https://builtin.com/company/powerlattice-inc)
5. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/powerlattice)

## Other roles at Powerlattice Technologies Inc.

- [Senior Digital Design Engineer](https://feeny.ai/job/senior-digital-design-engineer-powerlattice-technologies-inc-chandler-0kmj9dmzjxj1) — Chandler, AZ
- [Validation Engineering Lead](https://feeny.ai/job/validation-engineering-lead-powerlattice-technologies-inc-chandler-b7wkpc0tz8bh) — Chandler, AZ
- [Sr. Field Applications Engineer - Power Delivery](https://feeny.ai/job/sr-field-applications-engineer-power-delivery-powerlattice-technologies-inc-jff9zvs9n5kh) — Silicon Valley, CA
- [Senior/Staff Silicon Quality & Reliability Engineer](https://feeny.ai/job/senior-staff-silicon-quality-reliability-engineer-powerlattice-technologies-inc-kpa4nbwdn1wt) — Chandler, AZ
- [Power Delivery Solution Architect](https://feeny.ai/job/power-delivery-solution-architect-powerlattice-technologies-inc-chandler-jgqstzr686t5) — Chandler, AZ
- [Senior/Staff Analog IC Design Engineer](https://feeny.ai/job/senior-staff-analog-ic-design-engineer-powerlattice-technologies-inc-hq-am0zm00an62v) — HQ / Vancouver, Canada
- [Senior or Staff Hardware Design Engineer](https://feeny.ai/job/senior-or-staff-hardware-design-engineer-powerlattice-technologies-inc-chandler-ctnc8vpgay2h) — Chandler, AZ
- [Technical Program Manager](https://feeny.ai/job/technical-program-manager-physical-superintelligence-boston-y458ar5w9dx6) — Boston, MA
- [Technical Program Manager](https://feeny.ai/job/technical-program-manager-sardine-united-states-canada-1w4hn1gk919z) — United States / Canada
- [Technical Program Manager](https://feeny.ai/job/technical-program-manager-genesis-london-2mt52dmhg247) — London, United Kingdom