---
title: 'Validation Engineering Lead at Powerlattice Technologies Inc.'
canonical: 'https://feeny.ai/job/validation-engineering-lead-powerlattice-technologies-inc-chandler-b7wkpc0tz8bh'
type: 'job'
last_seen: '2026-09-07'
---

# Validation Engineering Lead at Powerlattice Technologies Inc.

- **Company:** Powerlattice Technologies Inc.
- **Location:** Chandler, AZ
- **Employment:** full-time
- **Work type:** hybrid
- **Posted:** 2026-08-19
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.ashbyhq.com/powerlattice/fa480a76-304e-4e2e-83dd-175108794692

## Job description

Validation Engineering Lead

Reports To: Head of Engineering

## About Us

Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.

## About the Role

We are seeking a highly skilled and hands-on Validation Engineering Lead to manage laboratory evaluation of chiplet power converters for AI and advanced computing. This involves test setup and automation, debugging, testing, and communication of results to the team. Giving leadership and guidance to the broader team is also necessary.

## Key Responsibilities

- Develop laboratory validation plans for products
- Create automated tests to align with validation plans
- Setup lab hardware to complete testing
- Debug hardware and lab test setups to complete testing
- Debug Powerlattice product during validation and communicate discovered issues to the team
- Assist scheduling team to create schedules for projects
- Document test results and communicate to the team
- Complete validation to align with schedules
- Lead and guide other team members as needed to complete validation

## Qualifications

This is an onsite role requiring 5 days a week onsite at our Chandler, AZ office. While we are primarily seeking candidates in Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.

- Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
- 10+ years of experience in validation of Integrated Circuits
- Proven track record of delivering validation plans
- Proven track record of completing validation plans with complex products
- Strong expertise with:
- Python scripting for lab automation
- Laboratory electronics equipment like power supplies, oscilloscopes, meters, etc.
- Ability to communicate validation plans, problems, results and propose solutions
- Strong debugging and problem-solving skills
- Leadership of validation projects with top-tier electronics companies
- Experience with silicon bring-up and post-silicon debug

## Compensation & Benefits

- Competitive base salary DOE
- Stock option grant
- Comprehensive benefits package including health, dental, vision, and 401(k)

## About Powerlattice Technologies Inc.

## Company Overview
- **One-liner**: PowerLattice reimagines power delivery for next-generation AI accelerators with the industry’s first power delivery chiplet, integrating voltage regulation directly into the processor package to break the AI power wall.
- **Entity Type**: Private (raised $25M in funding; stage not publicly specified)
- **Headquarters**: United States (specific city not publicly disclosed; offices in two US locations)
- **Founded**: Year not publicly available
- **Founders**: Dr. Peng Zou, Gang Ren, Sujith Dermal

## Core Business
- Primary industry: Semiconductor power delivery for AI accelerators, GPUs, and data-center processors
- Target customers: B2B – data center operators, AI hardware manufacturers, SoC designers
- Mission: “Reimagining power delivery for next-generation AI accelerators” by tightly integrating power and compute to achieve breakthrough performance, efficiency, and scalability.

## Products & Services
- **[Power Delivery Chiplet (Rainier micro-IVR architecture)]**: A monolithic chiplet that combines miniaturized on-die magnetic inductors, advanced control circuits, and a programmable software layer. It delivers voltage regulation directly inside the processor package, enabling 2-3X performance per watt, >50% reduction in power loss, and significantly extended system lifetime. Hardware product (chiplet) with software configurability.

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Total funding of $25M (announced on company website)
- **Notable Investors/Partners**: Investors include Steve Fu; board of directors includes Pat Gelsinger (former Intel CEO). Additional partners/backers not publicly detailed.
- **Growth Signals**: Early-stage company with a small team (10–20 employees per conflicting reports from BuiltIn); first-of-its-kind product targeting the urgent “power wall” problem in AI data centers; founders bring deep experience from Qualcomm, NUVIA, Intel, Huawei, and other top semiconductor firms.

## Competitive Advantages
- **On-die magnetic inductors** – miniaturized proprietary inductors integrated at the chip level, enabling tight coupling between power and compute.
- **Chiplet architecture** – scalable, configurable, and adaptable to any SoC power topology; can be embedded in substrates or interposers.
- **Order-of-magnitude reduction in power noise** and >50% reduction in effective compute power needs.
- **Performance uplift** – under fixed data center power budgets, translates into 2X or more raw performance uplift.
- **Founding team’s deep domain expertise** in power management, IVR, and high-volume IC design for tier-one customers (Apple, Samsung, Amazon).

## Strategic Focus
- Current priority: Productizing the power delivery chiplet and achieving design wins with major AI accelerator and GPU customers.
- Long-term direction: Scaling the chiplet architecture for next-generation data-center processors and expanding into broader high-performance computing markets.
- Focus on breaking the “power wall” that limits AI compute density and data center efficiency.

## Why Work Here
- **Culture**: Small, focused team working on hard problems at the intersection of hardware and innovation. Emphasizes curiosity, hands-on work, and real-world impact.
- **Work environment**: Remote-first with hybrid options; two US offices available. BuiltIn lists roles as “Remote Workspace” and “Hybrid”.
- **Perks**: Equity (stock options) offered. The company values thoughtful engineering and believes better power delivery can unlock new computing possibilities.
- **Engineering culture**: Deep technical challenges in analog/mixed-signal IC design, magnetic materials, system integration, and software. Opportunities to work with industry veterans and shape a groundbreaking product from early stage.

## Sources
1. [powerlatticeinc.com](https://powerlatticeinc.com/)
2. [powerlatticeinc.com/about](https://powerlatticeinc.com/about)
3. [powerlatticeinc.com/careers](https://powerlatticeinc.com/careers)
4. [builtin.com](https://builtin.com/company/powerlattice-inc)
5. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/powerlattice)

## Other roles at Powerlattice Technologies Inc.

- [Technical Program Manager](https://feeny.ai/job/technical-program-manager-powerlattice-technologies-inc-hq-vancouver-canada-gc6h651g9nrf) — HQ / Vancouver, Canada
- [Senior Digital Design Engineer](https://feeny.ai/job/senior-digital-design-engineer-powerlattice-technologies-inc-chandler-0kmj9dmzjxj1) — Chandler, AZ
- [Sr. Field Applications Engineer - Power Delivery](https://feeny.ai/job/sr-field-applications-engineer-power-delivery-powerlattice-technologies-inc-jff9zvs9n5kh) — Silicon Valley, CA
- [Senior/Staff Silicon Quality & Reliability Engineer](https://feeny.ai/job/senior-staff-silicon-quality-reliability-engineer-powerlattice-technologies-inc-kpa4nbwdn1wt) — Chandler, AZ
- [Power Delivery Solution Architect](https://feeny.ai/job/power-delivery-solution-architect-powerlattice-technologies-inc-chandler-jgqstzr686t5) — Chandler, AZ
- [Senior/Staff Analog IC Design Engineer](https://feeny.ai/job/senior-staff-analog-ic-design-engineer-powerlattice-technologies-inc-hq-am0zm00an62v) — HQ / Vancouver, Canada
- [Senior or Staff Hardware Design Engineer](https://feeny.ai/job/senior-or-staff-hardware-design-engineer-powerlattice-technologies-inc-chandler-ctnc8vpgay2h) — Chandler, AZ