---
title: 'Vice President of ASIC Engineering at Architect Labs'
canonical: 'https://feeny.ai/job/vice-president-of-asic-engineering-architect-labs-palo-alto-gmy5axfg5r3z'
type: 'job'
last_seen: '2026-11-11'
---

# Vice President of ASIC Engineering at Architect Labs

- **Company:** Architect Labs
- **Location:** Palo Alto, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-10-29
- **Last confirmed live:** 2026-11-11
- **Apply:** https://jobs.ashbyhq.com/architect/4125ab78-144c-4295-ab2e-f89f38bd5b6b

## Job description

## About Architect Labs

Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.

## What You'll Do

Own the ASIC methodology and end-to-end delivery of ambitious AI compute silicons, from microarchitecture and RTL through verification, physical design, signoff, and tapeout. Build a fundamentally faster, AI-native chip-development flow, using automation, intelligent agents, and data-driven feedback loops to accelerate design iteration, verification, closure, and engineering productivity. Lead a world-class team, set an uncompromising bar for PPA and silicon quality, and personally drive the most consequential technical and execution decisions.

## What We'd Like to See

- Repeated tapeout success: Direct leadership of multiple complex, production-volume ASIC or SoC programs, ideally at advanced process nodes.
- End-to-end ASIC mastery: Deep expertise spanning RTL, functional verification, synthesis, timing closure, physical implementation, DFT, signoff, and silicon bring-up.
- Methodology innovator: A track record of transforming design flows through automation, ML/AI-assisted EDA, verification productivity, or scalable engineering infrastructure—not merely operating established processes.
- Execution excellence: A demonstrated ability to deliver demanding programs with strong first-silicon outcomes and disciplined engineering tradeoffs.
- Elite team builder: A record of recruiting, developing, and leading world-class silicon engineers and technical leaders.
- Hands-on leadership: Credibility to resolve difficult cross-functional engineering problems personally while building processes that scale.

## What We Offer

Competitive compensation and meaningful equity, ownership of critical silicon programs, and the chance to build a world-class ASIC organization at the frontier of computing.

## About Architect Labs

## Company Overview
- **One-liner**: Architect Labs builds an AI system that explores, designs, and provably verifies custom chips for the world's most demanding AI workloads.
- **Entity Type**: Private (Seed stage – $24M raised)
- **Headquarters**: United States (specific city not publicly available)
- **Founded**: Not publicly available
- **Founders**: Ebrahim Hussain & Aaditya Subedi

## Core Business
- **Primary industry**: Semiconductor / AI chip design
- **Target customers**: B2B, Enterprise (companies needing custom silicon for frontier AI models)
- **Mission**: "Frontier AI for Silicon" – to enable custom chip co-design by rethinking the entire design process from first principles, accelerating development cycles and allowing organizations to own their hardware.

## Products & Services
- **AI-Driven Chip Co-Design System**: A self-improving AI platform that explores, designs, and formally verifies chip architectures. It co-optimizes compilers, system software, runtimes, and models, collapsing the distance between model evolution and silicon deployment. Type: AI platform / service.

## Market Standing
- **Valuation**: Not disclosed
- **Key Metric**: Total Funding – $24M seed round (June 2026)
- **Notable Investors/Partners**: Kindred Ventures (lead), TQ Ventures (lead), Race Capital, Together Fund, plus angel investors Jeff Dean, Srinivas Narayanan, Lukasz Kaiser, Aravind Srinivas, Kunle Olokotun, Trevor Blackwell, Dr. Alex Wissner-Gross, and executives from NVIDIA, Google, OpenAI, Perplexity.
- **Growth Signals**: 
  - Raised $24M seed in June 2026 from top-tier investors.
  - Assembled an elite team of researchers and engineers from Anthropic, xAI, Google DeepMind, Meta, Intel, and Samsung.
  - Founders have backgrounds at Apple’s silicon teams and Tesla’s AI5 chip program; collectively the team has taped out 80+ production chips and managed multi-billion-dollar product lines.

## Competitive Advantages
- **First-principles approach**: Not adapting AI to legacy chip workflows but rebuilding the entire chip design process from scratch.
- **Provable verification**: AI system includes formal verification, reducing risk and iteration in chip design.
- **Convergent expertise**: Rare combination of frontier AI research and deep silicon design experience within the same team.
- **Self-improving system**: The platform learns from each design cycle, creating a flywheel of faster, better designs.

## Strategic Focus
- **Democratize custom chip co-design**: Make specialized silicon accessible beyond a handful of incumbents.
- **Shorten chip development cycles**: Move from multi-year cycles to software-like velocity.
- **Unified design space**: Enable synchronous optimization of models, compilers, runtimes, and hardware.

## Why Work Here
- **Frontier work**: Tackle one of the most ambitious problems in modern technology – AI-driven chip design.
- **Small, exceptional team**: Emphasis on ownership ("Surface Area"), relentless execution, and long-term craft.
- **Culture**: Values include depth, intellectual rigor, and rapid prototyping. Team members come from top AI and semiconductor labs.
- **Location/Policy**: Not explicitly stated; likely US-based with some flexibility. The careers page highlights a fully in-person culture for deep collaboration (inferred from "small team" and "end-to-end ownership"). 
- **Perks**: Not detailed, but the work involves cutting-edge research and infrastructure.

## Sources
1. [architectlabs.com](https://architectlabs.com/)
2. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/architect)
3. [linkedin.com](https://www.linkedin.com/company/architectlab)
4. [kindredventures.com](https://kindredventures.com/announcement/architect-labs-democratizing-custom-chip-co-design/)

## Other roles at Architect Labs

- [Special Projects](https://feeny.ai/job/special-projects-architect-labs-palo-alto-20t2bt18hj3d) — Palo Alto, CA
- [Chief Architect](https://feeny.ai/job/chief-architect-architect-labs-palo-alto-1d0ca88ph9y2) — Palo Alto, CA
- [Member of Technical Staff - Physical Design](https://feeny.ai/job/member-of-technical-staff-physical-design-architect-labs-palo-alto-w148jdht2ctd) — Palo Alto, CA
- [Member of Technical Staff - Formal Verification](https://feeny.ai/job/member-of-technical-staff-formal-verification-architect-labs-palo-alto-1nmp3kygr0de) — Palo Alto, CA
- [Microarchitect / RTL Design - Memory Subsystem](https://feeny.ai/job/microarchitect-rtl-design-memory-subsystem-architect-labs-palo-alto-y0j0qnyxfc2j) — Palo Alto, CA
- [Microarchitect / RTL Design - Interconnect & Fabric](https://feeny.ai/job/microarchitect-rtl-design-interconnect-fabric-architect-labs-palo-alto-7eqe6bxeewnb) — Palo Alto, CA
- [Member of Technical Staff - Microarchitectural Validation](https://feeny.ai/job/member-of-technical-staff-microarchitectural-validation-architect-labs-palo-alto-03kf2jzzyf0m) — Palo Alto, CA
- [Member of Technical Staff - Microarchitectural Validation](https://feeny.ai/job/member-of-technical-staff-microarchitectural-validation-architect-labs-bengaluru-jf0s78hhyqrm) — Bengaluru, India
- [Member of Technical Staff - Software](https://feeny.ai/job/member-of-technical-staff-software-architect-labs-palo-alto-nhxbtrya6akb) — Palo Alto, CA
- [Member of Technical Staff - Formal Methods](https://feeny.ai/job/member-of-technical-staff-formal-methods-architect-labs-palo-alto-3np6mmsb8wz6) — Palo Alto, CA