RTL Power Engineer at Velaura (Santa Clara, CA)
Velaura· Santa Clara, CA· $200k–$300k·
Role details
Job description
Role Overview
We are looking for talented RTL Engineers to help build Velaura's next generation Physical AI SoC. You will work closely with architects, performance modelers, software engineers, verification engineers and physical design teams to turn architectural concepts into production silicon. In this role you will own power management of the SoC at every level, delivering silicon that meets its performance targets well within the power budgets allocated to it.
Responsibilities
- Design the on chip power management hardware for the Velaura SoC including digital power meters, activity monitors and throttlers.
- Design hardware and software control loops around temperature sensors that hold the die under a defined thermal limit.
- Design controls that keep the design under defined activity and average power limits as well as instantaneous di/dt limits.
- Work with architects, physical design and package teams on voltage droop behavior, power delivery and adaptive clocking response.
- Own clock and reset architecture including clock gating, PLL programming and management, and reset sequencing across power domains.
- Define and implement power state management including DVFS, power domains, retention and low power flows.
- Correlate power estimates across RTL, emulation and silicon, and build the telemetry that makes power and thermal behavior visible in the field.
- Work with firmware and software teams on the interfaces, policies and telemetry that drive power and thermal management.
Required Qualifications
- Strong grasp of the physics and electrical engineering behind average power, peak current, thermal behavior and voltage droop, and of how these concepts relate while remaining independent.
- Experience designing power management hardware such as digital power meters, throttlers, or thermal and current control loops.
- Understanding of di/dt, IR drop and power delivery network behavior, and their impact on timing margin.
- Experience with clock and reset architecture including clock gating, PLL management and reset sequencing.
- Working knowledge of Verilog or SystemVerilog and modern RTL design methodology.
- Experience with power estimation and analysis flows from RTL through gate level.
- Strong debugging and problem solving skills across hardware and software boundaries.
- BS or higher in Electrical Engineering, Computer Engineering or a related field.
Preferred Qualifications
- Experience with DVFS, adaptive voltage scaling, adaptive clocking or droop detection.
- Experience with UPF based low power design including power domains, retention and isolation.
- Experience correlating pre silicon power models against silicon measurement.
- Experience with thermal modeling, sensor placement, or package and board level thermal design.
- Experience with firmware or PMIC interfaces and power management software.
- Experience with power analysis tools such as PowerArtist, PrimePower or Joules.
- Familiarity with robotics, drones, autonomous vehicles or edge AI systems where power and thermal limits are tight.
- Experience using AI assisted design workflows to improve productivity and design exploration.
Why Velaura? Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world. This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.
Equal Employment Opportunity and Accommodations
Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans. Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: careers@velaura.ai. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.
Why work at Velaura
- Culture: Deep engineering DNA and systems-level thinking — the team is solving one of AI’s hardest physical constraints (power) with proven silicon technology
- Growth trajectory: Rapidly scaling startup (42 employees, +4.3% monthly headcount growth, $314M raised) with a clear path to becoming a key infrastructure provider for the AI era
- Leadership: Led by industry veterans (NUVIA, Apple, Google, Qualcomm) who have built billion-dollar silicon companies and products powering billions of devices
- Work environment: On-site roles in Santa Clara, CA; Austin, Texas; and Bangalore, India. Remote/hybrid policy not specified but multiple office locations suggest flexible collaboration.
- Impact: Opportunity to work on cutting-edge AI hardware design, from architecture through tape-out and deployment, with direct impact on the power efficiency of the world’s largest AI clusters
- Notable perks: Not publicly detailed, but the company’s focus on high-end engineering talent suggests competitive compensation, equity, and exposure to top-tier semiconductor and AI technology