
Head of Inference Performance Visibility at Etched (San Jose, CA)
Etched· San Jose, CA·
Role details
Etched at a glance
Transformer-specific ASICs and rack-scale systems that hardwire the transformer into silicon for faster, cheaper AI inference.
Etched designs transformer-specific ASICs and full rack-scale inference systems. Its Sohu chip hardwires the transformer architecture directly into silicon, trading a GPU's general-purpose flexibility for far higher throughput, lower latency, and better power efficiency on AI inference. Customers buy complete co-designed clusters, chip plus rack plus software, not standalone chips.
$800M raised · latest: $500M · led by Stripes · Dec 2025 (reported Jan 2026) · backed by Stripes, Peter Thiel, Ribbit Capital, VentureTech Alliance
Job description
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary We are hiring a Head of Performance Visibility to define how performance is understood across next-generation AI accelerator systems. Our ML accelerator platform spans custom silicon, supercomputing software, compiler stacks, runtime libraries, and distributed inference environments. Performance at this scale is no longer a device-level question — it is a high-performance distributed system problem. You will define the performance metrics that connect raw hardware signals to distributed workload context, ML cluster dynamics, pod communication patterns, and emergent bottlenecks. This role requires more than telemetry. You will establish new abstractions, structured counter ontologies, cross-layer event correlation frameworks, distributed time-alignment strategies, and scalable reasoning systems operating across nodes, racks, and clusters. Working at the intersection of hardware design, driver architecture, runtime systems, and ML infrastructure, you will shape how these layers expose and consume performance intelligence. This is a foundational role defining not just tooling, but how our platform reasons about efficiency, scalability, and system behavior for years to come.
Key Responsibilities besides Mentorship and Leadership
System-Level Performance Design
- Define the architectural approach for collecting and structuring telemetry across CPUs, drivers, interconnects, and multiple accelerators
- Design scalable models for correlating performance events across device and host boundaries
Cross-Layer Event Correlation
- Develop mechanisms to align hardware counters, runtime activity, communication phases, and workload semantics across model-layer execution into coherent, actionable insight
- Implement time synchronization and trace-alignment strategies across multi-device systems
Telemetry & Counter Modeling
- Define structured counter taxonomies separating base signals from derived metrics
- Design derived performance models bridging low-level hardware signals and workload-level behavior
- Influence instrumentation strategy for future hardware generations
Distributed Performance Reasoning
- Build tools that identify bottlenecks among multi-accelerator workloads across chips within hosts
- Build cluster-scale performance analysis for distributed inference across data center networks
Tooling & Insight Delivery
- Contribute to analysis engines and developer-facing tooling that transform raw telemetry into intuitive insight
- Shape how performance intelligence is surfaced to engineers debugging large-scale AI systems
You may be a good fit if you have
- Deep experience building complex systems at the intersection of hardware and software
- Personally envisioned and built significant portions of profiling, tracing, or observability systems — not solely defined requirements or product strategy
- Demonstrated ability to translate raw hardware signals into scalable, production-grade telemetry and analysis infrastructure
- Experience correlating time-series events across distributed systems
- Deep systems programming expertise (C++ or Rust), with a track record of shipping low-level infrastructure operating close to hardware or runtime systems
- Experience designing distributed correlation mechanisms, timestamp-alignment strategies, or performance modeling frameworks across multiple devices or hosts
- Experience designing distributed tracing or observability platforms at scale
- Experience with high-performance computing systems and large AI training clusters
- Experience with timestamp synchronization strategies and event alignment in distributed environments
- Experience with hardware counter design and instrumentation strategy
- Experience with performance modeling for large-scale ML workloads
- Experience leading cross-functional architectural initiatives spanning hardware and software teams
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2.5k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in our office
- Unlimited compute budget subject to ROI justification
How we’re different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
Why work at Etched
- Mission-driven, high-impact engineering: “Building the hardware for superintelligence” – the company is solving one of the hardest problems in compute (inference efficiency) with a focused team.
- Top-tier team and learning environment: Colleagues from Google, NVIDIA, Apple, Tesla, Broadcom, and Intel; exposure to full-stack chip-to-system design.
- In-office culture: All roles are in-office (Cupertino and San Jose, CA). The company emphasizes on-site collaboration for hardware development. Notable perks are not heavily advertised, but compensation is competitive for the AI hardware space (equity-heavy).
- Growth trajectory: 141% headcount growth YoY, hundreds of open roles, and a $5B valuation signal strong backing and career acceleration potential.
- Intellectual challenge: Work on chip simulation, RTL design, system validation, or software infrastructure for cutting-edge AI inference.