Low-Power Design Engineer at Voltai (Palo Alto, CA)Low-Power Design Engineer

Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.

Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.

You'll own power intent from architecture through signoff. You'll design and verify low-power architectures on real silicon programs with leading semiconductor companies while helping Voltai's AI learn power-aware design.

• Define power architecture and write UPF power intent for SoCs and IP.
• Implement and verify power gating, clock gating, multi-voltage domains, and retention.
• Run power-aware simulation, static low-power checks, and CDC/RDC analysis.
• Partner with RTL, physical design, and signoff teams on power estimation and closure.
• Build automation for power analysis and reporting.
• Evaluate AI-generated power intent and help define what correct looks like.

• 5+ years of low-power design or verification experience on production tapeouts.
• Expert UPF knowledge and experience with power-aware verification.
• Hands-on experience with tools like VC LP, Conformal Low Power, or PowerArtist.
• Experience with CDC/RDC tools (SpyGlass, Questa CDC, or similar).
• Python or Tcl scripting.

Bonus Points

• Experience with mobile, edge, or data-center power management.
• Formal verification of power intent.
• Interest in AI-assisted design tools.