Senior NVM Designer at Mythic (Palo Alto, CA)Senior NVM Designer

Mythic was founded in 2012 by University of Michigan researchers Mike Henry and Dave Fick, who set out to answer a simple question: what if a chip worked the way the human brain does? That first-principles thinking became analog compute-in-memory—an architecture that processes data where it lives instead of shuttling it back and forth across power-hungry pathways. Today, that architecture is proving its value. Mythic is the only analog compute-in-memory platform delivering 100x efficiency gains for the innovators who need AI inference at scale without the unsustainable energy cost, with technology proven across data center, automotive, robotics, and defense applications. Backed by an oversubscribed $125M raise from investors including Honda, Lockheed Martin, SoftBank, and DCVC, we're scaling toward a 1,024-chiplet architecture built for the largest LLM workloads in the data center—taking on the GPU status quo directly. We don't sell what's coming. We sell proven technology that works today, built on a fundamentally different approach to computing that we’ve been refining for over a decade. Intelligence is inevitable. How we get there is a choice. And Mythic is proving that power and efficiency were never a tradeoff to begin with.

- Participate in design and responsible for verifying complete IP macros specifically applicable for Mythic product architecture utilizing the available NVM technologies from foundries

- Involve in NVM architecture for optimum performance and area

- Design and verify the new circuits to handshake with the analog computation blocks

- Design, optimize and verify the NVM circuits including and not limited to high voltage generator block, x-path, y-path, test and peripheral circuits

- Participate in RNM and functional model of NVM circuits for verification

- Responsible for verifying the functional blocks and full chip level interfacing with NVM design

- Work closely with the validation engineers to expedite the silicon evaluation process

- Work closely with backend teams for the production qualification releases

- Ph.D. or MS degree in EE or related 5-10+ years industrial experience

- Hands-on experience in NVM embedded or NVM product design and verification

- Hands-on experience in NVM full chip circuit simulation setup, debugging, and verification

- Hands-on experience modeling circuits using Python, Verilog-A, and System Verilog Real Number Modeling

- Familiar and hands-on experience some or all memory circuit block design: decoder, high voltage switches, charge pumps, HV and LV regulator, bandgap, high performance low power sense amp, monitoring, and BIST capability

- Good understanding & knowledge of semiconductor device physics, and advanced process technology

- Experienced in multiple generations NVM tapeout activities, layout supervision, chip planning, silicon debugging

- Excellent communication skills, ability to work well across multi-functional teams

- Fluent in all major CAD tools: SPICE, Cadence, Verilog simulation software

- Some knowledge of scripting such as Python

- Must be a self-starter, detail-oriented, and team player