Compiler Engineer - Algorithmic Workloads Compilation at Mythic (Palo Alto, CA)Compiler Engineer - Algorithmic Workloads Compilation

Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications—whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from –40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense.

We’ve raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.

Help push the boundaries of what can run on our accelerator. You’ll design compiler IRs and lowering strategies to support algorithmic workloads with irregular or dynamic control flow—loops, branches, and iterative methods—going beyond static neural networks. Working side by side with hardware engineers, you’ll influence ISA and execution model co-design to unlock new algorithm classes on analog and digital subsystems. The result: a compiler that makes complex algorithms practical to deploy while staying seamless for developers.

Here's what you will do

• Extend compiler IRs to represent algorithms not easily captured in DNN graphs including control flow and iterative computation
• Develop compilation strategies that unify analog compute with digital subsystems while maintaining performance and correctness
• Prototype and optimize algorithms with irregular or dynamic control flow in compiler IRs, applying techniques such as vectorization, predication, and scheduling
• Collaborate with hardware engineers to co-design ISA and features that improve support for algorithmic workloads
• Define a roadmap for higher-level programming abstractions that simplify prototyping and accelerate deployment

Here's the background we hope you will have

• 3+ years of professional experience in compilers or high-performance systems software
• Proficiency in modern C++ (C++14/17/20) and Python
• Familiarity with compiler IRs (e.g., MLIR, LLVM, or equivalent) and their use representing complex program structures
• Solid foundation in program analysis and optimization techniques (e.g., SSA form, loop optimizations, vectorization)

The following would be nice to have, but is not required

• Hands-on experience developing MLIR or LLVM dialects for control flow (e.g. scf, cf) or affine/polyhedral representations.
• Background in compiler-hardware co-design: working with hardware designers to refine ISA or execution models for efficiency
• Proven ability to prototype irregular or control-flow algorithms in compiler IRs and optimize them for performance and resource constraints
• Experience extending ML compiler stacks (ONNX, IREE, XLA, PyTorch, TVM) to support workloads beyond DNNs

• The opportunity to make algorithmic and control-flow-heavy workloads practical on novel accelerator hardware.
• A role that bridges compiler design and hardware co-design, shaping both the IR and the accelerator architecture.
• A collaborative, innovative team that values engineering rigor, continuous integration, and user-focused design.
• Competitive compensation, equity, and benefits package.